skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036033/0231   Pages: 152
Recorded: 06/29/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 25
1
Patent #:
6438726
Issue Dt:
08/20/2002
Application #:
09314575
Filing Dt:
05/18/1999
Title:
METHOD OF DUAL USE OF NON-VOLATILE MEMORY FOR ERROR CORRECTION
2
Patent #:
6452441
Issue Dt:
09/17/2002
Application #:
09411169
Filing Dt:
10/01/1999
Title:
LOW THRESHOLD VOLTAGE DEVICE WITH CHARGE PUMP FOR REDUCING STANDBY CURRENT IN AN INTEGRATED CIRCUIT HAVING REDUCED SUPPLY VOLTAGE
3
Patent #:
6448609
Issue Dt:
09/10/2002
Application #:
09429244
Filing Dt:
10/28/1999
Title:
METHOD AND SYSTEM FOR PROVIDINNG A POLYSILICON STRINGER MONITOR
4
Patent #:
6441418
Issue Dt:
08/27/2002
Application #:
09430848
Filing Dt:
11/01/1999
Title:
SPACER NARROWED, DUAL WIDTH CONTACT FOR CHARGE GAIN REDUCTION
5
Patent #:
6455888
Issue Dt:
09/24/2002
Application #:
09506298
Filing Dt:
02/17/2000
Title:
ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
6
Patent #:
6448606
Issue Dt:
09/10/2002
Application #:
09513261
Filing Dt:
02/24/2000
Title:
SEMICONDUCTOR WITH INCREASED GATE COUPLING COEFFICIENT
7
Patent #:
6456170
Issue Dt:
09/24/2002
Application #:
09538720
Filing Dt:
03/30/2000
Title:
COMPARATOR AND VOLTAGE CONTROLLED OSCILLATOR CIRCUIT
8
Patent #:
6448594
Issue Dt:
09/10/2002
Application #:
09539307
Filing Dt:
03/30/2000
Title:
METHOD AND SYSTEM FOR PROCESSING A SEMICONDUCTOR DEVICE
9
Patent #:
6445051
Issue Dt:
09/03/2002
Application #:
09563797
Filing Dt:
05/02/2000
Title:
METHOD AND SYSTEM FOR PROVIDING CONTACTS WITH GREATER TOLERANCE FOR MISALIGNMENT IN A FLASH MEMORY
10
Patent #:
6452225
Issue Dt:
09/17/2002
Application #:
09617820
Filing Dt:
07/17/2000
Title:
Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride
11
Patent #:
6448608
Issue Dt:
09/10/2002
Application #:
09631894
Filing Dt:
08/04/2000
Title:
NOVEL CAPPING LAYER
12
Patent #:
6438041
Issue Dt:
08/20/2002
Application #:
09668100
Filing Dt:
09/22/2000
Title:
NEGATIVE VOLTAGE REGULATION
13
Patent #:
6452840
Issue Dt:
09/17/2002
Application #:
09693649
Filing Dt:
10/21/2000
Title:
FEEDBACK METHOD TO OPTIMIZE ELECTRIC FIELD DURING CHANNEL ERASE OF FLASH MEMORY DEVICES
14
Patent #:
6440789
Issue Dt:
08/27/2002
Application #:
09704026
Filing Dt:
11/01/2000
Title:
PHOTORESIST SPACER PROCESS SIMPLIFICATION TO ELIMINATE THE STANDARD POLYSILICON OR OXIDE SPACER PROCESS FOR FLASH MEMORY CIRCUITS
15
Patent #:
6452449
Issue Dt:
09/17/2002
Application #:
09707879
Filing Dt:
11/08/2000
Title:
GAIN VARIABLE AMPLIFIER
16
Patent #:
6449190
Issue Dt:
09/10/2002
Application #:
09764965
Filing Dt:
01/17/2001
Title:
ADAPTIVE REFERENCE CELLS FOR A MEMORY DEVICE
17
Patent #:
6445030
Issue Dt:
09/03/2002
Application #:
09772600
Filing Dt:
01/30/2001
Title:
FLASH MEMORY ERASE SPEED BY FLUORINE IMPLANT OR FLUORINATION
18
Patent #:
6442074
Issue Dt:
08/27/2002
Application #:
09795854
Filing Dt:
02/28/2001
Title:
TAILORED ERASE METHOD USING HIGHER PROGRAM VT AND HIGHER NEGATIVE GATE ERASE
19
Patent #:
6456533
Issue Dt:
09/24/2002
Application #:
09796282
Filing Dt:
02/28/2001
Publication #:
US20020159293
Pub Dt:
10/31/2002
Title:
HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
20
Patent #:
6455373
Issue Dt:
09/24/2002
Application #:
09834419
Filing Dt:
04/12/2001
Title:
SEMICONDUCTOR DEVICE HAVING GATE EDGES PROTECTED FROM CHARGE GAIN/LOSS
21
Patent #:
6456531
Issue Dt:
09/24/2002
Application #:
09884402
Filing Dt:
06/19/2001
Title:
METHOD OF DRAIN AVALANCHE PROGRAMMING OF A NON-VOLATILE MEMORY CELL
22
Patent #:
6456536
Issue Dt:
09/24/2002
Application #:
09884409
Filing Dt:
06/19/2001
Title:
METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS
23
Patent #:
6449188
Issue Dt:
09/10/2002
Application #:
09884565
Filing Dt:
06/19/2001
Title:
LOW COLUMN LEAKAGE NOR FLASH ARRAY-DOUBLE CELL IMPLEMENTATION
24
Patent #:
6456141
Issue Dt:
09/24/2002
Application #:
09922764
Filing Dt:
08/07/2001
Publication #:
US20020101270
Pub Dt:
08/01/2002
Title:
CURRENT PULSE RECEIVING CIRCUIT
25
Patent #:
6440797
Issue Dt:
08/27/2002
Application #:
09966702
Filing Dt:
09/28/2001
Title:
NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN A FABRICATION OF SONOS FLASH MEMORY
Assignor
1
SPANSION, LLC
Exec Dt:
06/01/2015
Assignee
1
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

Search Results as of: 05/28/2024 03:50 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT