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Total properties:
13
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09644928
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Filing Dt:
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08/23/2000
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Title:
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Reduced skew timing scheme for write circuitry used in memory circuits
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09651939
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Filing Dt:
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08/31/2000
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Title:
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LOCAL WRITE DRIVER CIRCUIT FOR AN INTEGRATED CIRCUIT DEVICE INCORPORATING EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (DRAM)
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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10074375
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Filing Dt:
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02/11/2002
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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LOOK-AHEAD REFRESH FOR AN INTEGRATED CIRCUIT MEMORY
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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10099333
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Filing Dt:
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03/14/2002
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Title:
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PRECHARGE AND REFERENCE VOLTAGE TECHNIQUE FOR DYNAMIC RANDOM ACCESS MEMORIES
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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10100151
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Filing Dt:
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03/18/2002
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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DATA PATH DECODING TECHNIQUE FOR AN EMBEDDED MEMORY ARRAY
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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10125756
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Filing Dt:
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04/18/2002
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Title:
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AUTOMATIC DELAY TECHNIQUE FOR EARLY READ AND WRITE OPERATIONS IN SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORIES
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10136261
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Filing Dt:
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05/01/2002
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Publication #:
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Pub Dt:
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08/14/2003
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Title:
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REFRESH INITIATED PRECHARGE TECHNIQUE FOR DYNAMIC RANDOM ACCESS MEMORY ARRAYS USING LOOK-AHEAD REFRESH
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10289736
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Filing Dt:
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11/07/2002
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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ASYNCHRONOUS INPUT DATA PATH TECHNIQUE FOR INCREASING SPEED AND REDUCING LATENCY IN INTEGRATED CIRCUIT DEVICES INCORPORATING DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARRAYS AND EMBEDDED DRAM
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Patent #:
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Issue Dt:
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01/09/2007
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Application #:
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10345735
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Filing Dt:
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01/16/2003
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Publication #:
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Pub Dt:
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07/22/2004
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Title:
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REDUCED GATE DELAY MULTIPLEXED INTERFACE AND OUTPUT BUFFER CIRCUIT FOR INTEGRATED CIRCUIT DEVICES INCORPORATING RANDOM ACCESS MEMORY ARRAYS
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10345736
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Filing Dt:
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01/16/2003
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Publication #:
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Pub Dt:
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07/22/2004
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Title:
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BITLINE REFERENCE VOLTAGE CIRCUIT
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10358668
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Filing Dt:
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02/05/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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BANDGAP REFERENCE CIRCUIT
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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10374562
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Filing Dt:
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02/25/2003
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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DATA PATH DECODING TECHNIQUE FOR AN EMBEDDED MEMORY ARRAY
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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11081191
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Filing Dt:
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03/16/2005
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Title:
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DUAL WORD LINE MODE FOR DRAMS
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