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Reel/Frame:019817/0236   Pages: 27
Recorded: 09/12/2007
Attorney Dkt #:62600
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 52
1
Patent #:
7432524
Issue Dt:
10/07/2008
Application #:
10936903
Filing Dt:
09/09/2004
Publication #:
US20050029511
Pub Dt:
02/10/2005
Title:
INTEGRATED CIRCUIT COMPRISING AN ACTIVE OPTICAL DEVICE HAVING AN ENERGY BAND ENGINEERED SUPERLATTICE
2
Patent #:
7446334
Issue Dt:
11/04/2008
Application #:
10936913
Filing Dt:
09/09/2004
Publication #:
US20050029509
Pub Dt:
02/10/2005
Title:
ELECTRONIC DEVICE COMPRISING ACTIVE OPTICAL DEVICES WITH AN ENERGY BAND ENGINEERED SUPERLATTICE
3
Patent #:
NONE
Issue Dt:
Application #:
10936933
Filing Dt:
09/09/2004
Publication #:
US20050032247
Pub Dt:
02/10/2005
Title:
Method for making an integrated circuit comprising an active optical device having an energy band engineered superlattice
4
Patent #:
7279699
Issue Dt:
10/09/2007
Application #:
10937071
Filing Dt:
09/09/2004
Publication #:
US20050031247
Pub Dt:
02/10/2005
Title:
INTEGRATED CIRCUIT COMPRISING A WAVEGUIDE HAVING AN ENERGY BAND ENGINEERED SUPERLATTICE
5
Patent #:
NONE
Issue Dt:
Application #:
10937072
Filing Dt:
09/09/2004
Publication #:
US20050029510
Pub Dt:
02/10/2005
Title:
Method for making electronic device comprising active optical devices with an energy band engineered superlattice
6
Patent #:
7436026
Issue Dt:
10/14/2008
Application #:
10940426
Filing Dt:
09/14/2004
Publication #:
US20050087737
Pub Dt:
04/28/2005
Title:
SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE CHANNEL VERTICALLY STEPPED ABOVE SOURCE AND DRAIN REGIONS
7
Patent #:
7288457
Issue Dt:
10/30/2007
Application #:
10940594
Filing Dt:
09/14/2004
Publication #:
US20050118767
Pub Dt:
06/02/2005
Title:
METHOD FOR MAKING SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE WITH UPPER PORTIONS EXTENDING ABOVE ADJACENT UPPER PORTIONS OF SOURCE AND DRAIN REGIONS
8
Patent #:
7279701
Issue Dt:
10/09/2007
Application #:
10941062
Filing Dt:
09/14/2004
Publication #:
US20050110003
Pub Dt:
05/26/2005
Title:
SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE WITH UPPER PORTIONS EXTENDING ABOVE ADJACENT UPPER PORTIONS OF SOURCE AND DRAIN REGIONS
9
Patent #:
7435988
Issue Dt:
10/14/2008
Application #:
11042270
Filing Dt:
01/25/2005
Publication #:
US20050173697
Pub Dt:
08/11/2005
Title:
SEMICONDUCTOR DEVICE INCLUDING A MOSFET HAVING A BAND-ENGINEERED SUPERLATTICE WITH A SEMICONDUCTOR CAP LAYER PROVIDING A CHANNEL
10
Patent #:
7265002
Issue Dt:
09/04/2007
Application #:
11042272
Filing Dt:
01/25/2005
Publication #:
US20050173696
Pub Dt:
08/11/2005
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A MOSFET HAVING A BAND-ENGINEERED SUPERLATTICE WITH A SEMICONDUCTOR CAP LAYER PROVIDING A CHANNEL
11
Patent #:
7303948
Issue Dt:
12/04/2007
Application #:
11089950
Filing Dt:
03/25/2005
Publication #:
US20050184286
Pub Dt:
08/25/2005
Title:
SEMICONDUCTOR DEVICE INCLUDING MOSFET HAVING BAND-ENGINEERED SUPERLATTICE
12
Patent #:
7446002
Issue Dt:
11/04/2008
Application #:
11136747
Filing Dt:
05/25/2005
Publication #:
US20060019454
Pub Dt:
01/26/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE COMPRISING A SUPERLATTICE DIELECTRIC INTERFACE LAYER
13
Patent #:
NONE
Issue Dt:
Application #:
11136748
Filing Dt:
05/25/2005
Publication #:
US20050282330
Pub Dt:
12/22/2005
Title:
Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
14
Patent #:
NONE
Issue Dt:
Application #:
11136757
Filing Dt:
05/25/2005
Publication #:
US20050279991
Pub Dt:
12/22/2005
Title:
Semiconductor device including a superlattice having at least one group of substantially undoped layers
15
Patent #:
NONE
Issue Dt:
Application #:
11136881
Filing Dt:
05/25/2005
Publication #:
US20060011905
Pub Dt:
01/19/2006
Title:
Semiconductor device comprising a superlattice dielectric interface layer
16
Patent #:
NONE
Issue Dt:
Application #:
11380987
Filing Dt:
05/01/2006
Publication #:
US20060220118
Pub Dt:
10/05/2006
Title:
SEMICONDUCTOR DEVICE INCLUDING A DOPANT BLOCKING SUPERLATTICE
17
Patent #:
NONE
Issue Dt:
Application #:
11380992
Filing Dt:
05/01/2006
Publication #:
US20060273299
Pub Dt:
12/07/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A DOPANT BLOCKING SUPERLATTICE
18
Patent #:
7659539
Issue Dt:
02/09/2010
Application #:
11381787
Filing Dt:
05/05/2006
Publication #:
US20060243963
Pub Dt:
11/02/2006
Title:
SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE MEMORY CELL WITH A SUPERLATTICE CHANNEL
19
Patent #:
NONE
Issue Dt:
Application #:
11381794
Filing Dt:
05/05/2006
Publication #:
US20060263980
Pub Dt:
11/23/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE MEMORY CELL WITH A SUPERLATTICE CHANNEL
20
Patent #:
7586116
Issue Dt:
09/08/2009
Application #:
11381835
Filing Dt:
05/05/2006
Publication #:
US20060261327
Pub Dt:
11/23/2006
Title:
SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR CONFIGURATION AND A SUPERLATTICE
21
Patent #:
NONE
Issue Dt:
Application #:
11381850
Filing Dt:
05/05/2006
Publication #:
US20060243964
Pub Dt:
11/02/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR CONFIGURATION AND A SUPERLATTICE
22
Patent #:
7531850
Issue Dt:
05/12/2009
Application #:
11420876
Filing Dt:
05/30/2006
Publication #:
US20060202189
Pub Dt:
09/14/2006
Title:
SEMICONDUCTOR DEVICE INCLUDING A MEMORY CELL WITH A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE
23
Patent #:
NONE
Issue Dt:
Application #:
11420891
Filing Dt:
05/30/2006
Publication #:
US20060231857
Pub Dt:
10/19/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A MEMORY CELL WITH A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE
24
Patent #:
7586165
Issue Dt:
09/08/2009
Application #:
11421234
Filing Dt:
05/31/2006
Publication #:
US20060226502
Pub Dt:
10/12/2006
Title:
MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE INCLUDING A SUPERLATTICE
25
Patent #:
NONE
Issue Dt:
Application #:
11421263
Filing Dt:
05/31/2006
Publication #:
US20060223215
Pub Dt:
10/05/2006
Title:
Method for Making a Microelectromechanical Systems (MEMS) Device Including a Superlattice
26
Patent #:
NONE
Issue Dt:
Application #:
11425201
Filing Dt:
06/20/2006
Publication #:
US20060267130
Pub Dt:
11/30/2006
Title:
Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
27
Patent #:
7514328
Issue Dt:
04/07/2009
Application #:
11425209
Filing Dt:
06/20/2006
Publication #:
US20060270169
Pub Dt:
11/30/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH A SUPERLATTICE THEREBETWEEN
28
Patent #:
NONE
Issue Dt:
Application #:
11426976
Filing Dt:
06/28/2006
Publication #:
US20060292765
Pub Dt:
12/28/2006
Title:
Method for Making a FINFET Including a Superlattice
29
Patent #:
7491587
Issue Dt:
02/17/2009
Application #:
11428003
Filing Dt:
06/30/2006
Publication #:
US20060292818
Pub Dt:
12/28/2006
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR (SOI) CONFIGURATION AND INCLUDING A SUPERLATTICE ON A THIN SEMICONDUCTOR LAYER
30
Patent #:
NONE
Issue Dt:
Application #:
11428015
Filing Dt:
06/30/2006
Publication #:
US20060289049
Pub Dt:
12/28/2006
Title:
Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
31
Patent #:
7612366
Issue Dt:
11/03/2009
Application #:
11457256
Filing Dt:
07/13/2006
Publication #:
US20070007508
Pub Dt:
01/11/2007
Title:
SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE LAYER ABOVE A STRESS LAYER
32
Patent #:
NONE
Issue Dt:
Application #:
11457263
Filing Dt:
07/13/2006
Publication #:
US20070010040
Pub Dt:
01/11/2007
Title:
Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
33
Patent #:
7531828
Issue Dt:
05/12/2009
Application #:
11457269
Filing Dt:
07/13/2006
Publication #:
US20070012909
Pub Dt:
01/18/2007
Title:
SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE BETWEEN AT LEAST ONE PAIR OF SPACED APART STRESS REGIONS
34
Patent #:
NONE
Issue Dt:
Application #:
11457276
Filing Dt:
07/13/2006
Publication #:
US20070015344
Pub Dt:
01/18/2007
Title:
Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
35
Patent #:
7598515
Issue Dt:
10/06/2009
Application #:
11457286
Filing Dt:
07/13/2006
Publication #:
US20070012912
Pub Dt:
01/18/2007
Title:
SEMICONDUCTOR DEVICE INCLUDING A STRAINED SUPERLATTICE AND OVERLYING STRESS LAYER AND RELATED METHODS
36
Patent #:
NONE
Issue Dt:
Application #:
11457293
Filing Dt:
07/13/2006
Publication #:
US20070020860
Pub Dt:
01/25/2007
Title:
Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
37
Patent #:
NONE
Issue Dt:
Application #:
11457299
Filing Dt:
07/13/2006
Publication #:
US20070012910
Pub Dt:
01/18/2007
Title:
Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
38
Patent #:
NONE
Issue Dt:
Application #:
11457315
Filing Dt:
07/13/2006
Publication #:
US20070020833
Pub Dt:
01/25/2007
Title:
Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
39
Patent #:
7531829
Issue Dt:
05/12/2009
Application #:
11534298
Filing Dt:
09/22/2006
Publication #:
US20070012911
Pub Dt:
01/18/2007
Title:
SEMICONDUCTOR DEVICE INCLUDING REGIONS OF BAND-ENGINEERED SEMICONDUCTOR SUPERLATTICE TO REDUCE DEVICE-ON RESISTANCE
40
Patent #:
7535041
Issue Dt:
05/19/2009
Application #:
11534343
Filing Dt:
09/22/2006
Publication #:
US20070012999
Pub Dt:
01/18/2007
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING REGIONS OF BAND-ENGINEERED SEMICONDUCTOR SUPERLATTICE TO REDUCE DEVICE-ON RESISTANCE
41
Patent #:
NONE
Issue Dt:
Application #:
11534796
Filing Dt:
09/25/2006
Publication #:
US20070063185
Pub Dt:
03/22/2007
Title:
Semiconductor device including a front side strained superlattice layer and a back side stress layer
42
Patent #:
NONE
Issue Dt:
Application #:
11534819
Filing Dt:
09/25/2006
Publication #:
US20070063186
Pub Dt:
03/22/2007
Title:
Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
43
Patent #:
NONE
Issue Dt:
Application #:
11614477
Filing Dt:
12/21/2006
Publication #:
US20070158640
Pub Dt:
07/12/2007
Title:
ELECTRONIC DEVICE INCLUDING A POLED SUPERLATTICE HAVING A NET ELECTRICAL DIPOLE MOMENT
44
Patent #:
7517702
Issue Dt:
04/14/2009
Application #:
11614513
Filing Dt:
12/21/2006
Publication #:
US20070161138
Pub Dt:
07/12/2007
Title:
METHOD FOR MAKING AN ELECTRONIC DEVICE INCLUDING A POLED SUPERLATTICE HAVING A NET ELECTRICAL DIPOLE MOMENT
45
Patent #:
NONE
Issue Dt:
Application #:
11614535
Filing Dt:
12/21/2006
Publication #:
US20070187667
Pub Dt:
08/16/2007
Title:
ELECTRONIC DEVICE INCLUDING A SELECTIVELY POLABLE SUPERLATTICE
46
Patent #:
NONE
Issue Dt:
Application #:
11614559
Filing Dt:
12/21/2006
Publication #:
US20070166928
Pub Dt:
07/19/2007
Title:
METHOD FOR MAKING AN ELECTRONIC DEVICE INCLUDING A SELECTIVELY POLABLE SUPERLATTICE
47
Patent #:
7880161
Issue Dt:
02/01/2011
Application #:
11675833
Filing Dt:
02/16/2007
Publication #:
US20080197340
Pub Dt:
08/21/2008
Title:
MULTIPLE-WAVELENGTH OPTO-ELECTRONIC DEVICE INCLUDING A SUPERLATTICE
48
Patent #:
7863066
Issue Dt:
01/04/2011
Application #:
11675846
Filing Dt:
02/16/2007
Publication #:
US20080197341
Pub Dt:
08/21/2008
Title:
METHOD FOR MAKING A MULTIPLE-WAVELENGTH OPTO-ELECTRONIC DEVICE INCLUDING A SUPERLATTICE
49
Patent #:
7718996
Issue Dt:
05/18/2010
Application #:
11677098
Filing Dt:
02/21/2007
Publication #:
US20070194298
Pub Dt:
08/23/2007
Title:
SEMICONDUCTOR DEVICE COMPRISING A LATTICE MATCHING LAYER
50
Patent #:
7700447
Issue Dt:
04/20/2010
Application #:
11677099
Filing Dt:
02/21/2007
Publication #:
US20070197006
Pub Dt:
08/23/2007
Title:
METHOD FOR MAKING A SEMICONDUCTOR DEVICE COMPRISING A LATTICE MATCHING LAYER
51
Patent #:
NONE
Issue Dt:
Application #:
11687422
Filing Dt:
03/16/2007
Publication #:
US20080012004
Pub Dt:
01/17/2008
Title:
SPINTRONIC DEVICES WITH CONSTRAINED SPINTRONIC DOPANT
52
Patent #:
7625767
Issue Dt:
12/01/2009
Application #:
11687430
Filing Dt:
03/16/2007
Publication #:
US20070238274
Pub Dt:
10/11/2007
Title:
METHODS OF MAKING SPINTRONIC DEVICES WITH CONSTRAINED SPINTRONIC DOPANT
Assignor
1
RJ MEARS, LLC
Exec Dt:
03/14/2007
Assignee
1
MEARS TECHNOLOGIES, INC.
1100 WINTER STREET
SUITE 4700
WALTHAM, MASSACHUSETTS 02451
Correspondence name and address
CHRISTOPHER F. REGAN
255 S. ORANGE AVE.
SUITE 1401
ORLANDO, FL 32801-3460

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