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Reel/Frame:052850/0237   Pages: 31
Recorded: 06/05/2020
Attorney Dkt #:2515.5050
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 250
Page 2 of 3
Pages: 1 2 3
1
Patent #:
Issue Dt:
09/17/2013
Application #:
12822405
Filing Dt:
06/24/2010
Publication #:
Pub Dt:
12/29/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRENCHES AND METHOD OF MANUFACTURE THEREOF
2
Patent #:
Issue Dt:
04/02/2013
Application #:
12822504
Filing Dt:
06/24/2010
Publication #:
Pub Dt:
12/29/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECT STRUCTURE ON LEADFRAME
3
Patent #:
Issue Dt:
03/05/2013
Application #:
12822659
Filing Dt:
06/24/2010
Publication #:
Pub Dt:
12/29/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STAND-OFF AND METHOD OF MANUFACTURE THEREOF
4
Patent #:
Issue Dt:
01/21/2014
Application #:
12823079
Filing Dt:
06/24/2010
Publication #:
Pub Dt:
10/21/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE AND METHOD OF MANUFACTURE THEREOF
5
Patent #:
Issue Dt:
04/02/2013
Application #:
12834176
Filing Dt:
07/12/2010
Publication #:
Pub Dt:
11/04/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING
6
Patent #:
Issue Dt:
02/04/2014
Application #:
12837562
Filing Dt:
07/16/2010
Publication #:
Pub Dt:
01/19/2012
Title:
Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die
7
Patent #:
Issue Dt:
11/06/2012
Application #:
12854306
Filing Dt:
08/11/2010
Publication #:
Pub Dt:
02/16/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED LEAD AND METHOD OF MANUFACTURE THEREOF
8
Patent #:
Issue Dt:
08/06/2013
Application #:
12856288
Filing Dt:
08/13/2010
Publication #:
Pub Dt:
04/07/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHAPED LEAD AND METHOD OF MANUFACTURE THEREOF
9
Patent #:
Issue Dt:
07/23/2013
Application #:
12858163
Filing Dt:
08/17/2010
Publication #:
Pub Dt:
02/23/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET CONDUCTIVE PILLARS OVER FIRST SUBSTRATE ALIGNED TO VERTICALLY OFFSET BOT INTERCONNECT SITES FORMED OVER SECOND SUBSTRATE
10
Patent #:
Issue Dt:
05/07/2013
Application #:
12874827
Filing Dt:
09/02/2010
Publication #:
Pub Dt:
03/08/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE LEADS FROM BASE SUBSTRATE AS STANDOFF FOR STACKING SEMICONDUCTOR DIE
11
Patent #:
Issue Dt:
07/16/2013
Application #:
12875496
Filing Dt:
09/03/2010
Publication #:
Pub Dt:
12/23/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER AND METHOD FOR MANUFACTURING THEREOF
12
Patent #:
Issue Dt:
04/02/2013
Application #:
12875998
Filing Dt:
09/03/2010
Publication #:
Pub Dt:
03/08/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOUNTING
13
Patent #:
Issue Dt:
11/06/2012
Application #:
12878661
Filing Dt:
09/09/2010
Publication #:
Pub Dt:
03/15/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH CAVITIES FORMED THROUGH ETCH-RESISTANT CONDUCTIVE LAYER FOR BUMP LOCKING
14
Patent #:
Issue Dt:
11/06/2012
Application #:
12881983
Filing Dt:
09/14/2010
Publication #:
Pub Dt:
03/15/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
15
Patent #:
Issue Dt:
02/19/2013
Application #:
12882067
Filing Dt:
09/14/2010
Publication #:
Pub Dt:
03/15/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
16
Patent #:
Issue Dt:
03/26/2013
Application #:
12884073
Filing Dt:
09/16/2010
Publication #:
Pub Dt:
03/22/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADDLE MOLDING AND METHOD OF MANUFACTURE THEREOF
17
Patent #:
Issue Dt:
06/18/2013
Application #:
12884134
Filing Dt:
09/16/2010
Publication #:
Pub Dt:
03/22/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
18
Patent #:
Issue Dt:
06/11/2013
Application #:
12885137
Filing Dt:
09/17/2010
Publication #:
Pub Dt:
03/22/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST AND METHOD OF MANUFACTURE THEREOF
19
Patent #:
Issue Dt:
03/19/2013
Application #:
12885831
Filing Dt:
09/20/2010
Publication #:
Pub Dt:
03/22/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DAM MATERIAL WITH OPENINGS AROUND SEMICONDUCTOR DIE FOR MOLD UNDERFILL USING DISPENSER AND VACUUM ASSIST
20
Patent #:
Issue Dt:
01/08/2013
Application #:
12887811
Filing Dt:
09/22/2010
Publication #:
Pub Dt:
03/22/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE TSV WITH INSULATING ANNULAR RING
21
Patent #:
Issue Dt:
06/04/2013
Application #:
12890338
Filing Dt:
09/24/2010
Publication #:
Pub Dt:
03/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL AND METHOD OF MANUFACTURE THEREOF
22
Patent #:
Issue Dt:
08/27/2013
Application #:
12890409
Filing Dt:
09/24/2010
Publication #:
Pub Dt:
03/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
23
Patent #:
Issue Dt:
02/04/2014
Application #:
12891232
Filing Dt:
09/27/2010
Publication #:
Pub Dt:
03/29/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE STRUCTURE AROUND SEMICONDUCTOR DIE FOR LOCALIZED PLANARIZATION OF INSULATING LAYER
24
Patent #:
Issue Dt:
02/05/2013
Application #:
12912728
Filing Dt:
10/26/2010
Publication #:
Pub Dt:
02/17/2011
Title:
DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
25
Patent #:
Issue Dt:
02/19/2013
Application #:
12912730
Filing Dt:
10/26/2010
Publication #:
Pub Dt:
02/17/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH IMAGE SENSOR SYSTEM
26
Patent #:
Issue Dt:
12/11/2012
Application #:
12916758
Filing Dt:
11/01/2010
Publication #:
Pub Dt:
02/24/2011
Title:
ULTRA THIN BUMPED WAFER WITH UNDER-FILM
27
Patent #:
Issue Dt:
02/26/2013
Application #:
12947442
Filing Dt:
11/16/2010
Publication #:
Pub Dt:
05/17/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME ELECTRICALLY CONNECTED TO EMBEDDED SEMICONDUCTOR DIE
28
Patent #:
Issue Dt:
04/16/2013
Application #:
12948756
Filing Dt:
11/17/2010
Publication #:
Pub Dt:
05/17/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FOLDABLE SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
29
Patent #:
Issue Dt:
02/12/2013
Application #:
12950631
Filing Dt:
11/19/2010
Publication #:
Pub Dt:
05/24/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
30
Patent #:
Issue Dt:
07/02/2013
Application #:
12953812
Filing Dt:
11/24/2010
Publication #:
Pub Dt:
05/24/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH RECESSES FOR CAPTURING BUMPED SEMICONDUCTOR DIE
31
Patent #:
Issue Dt:
08/06/2013
Application #:
12957339
Filing Dt:
11/30/2010
Publication #:
Pub Dt:
05/31/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-ROW LEADS AND METHOD OF MANUFACTURE THEREOF
32
Patent #:
Issue Dt:
08/13/2013
Application #:
12957361
Filing Dt:
11/30/2010
Publication #:
Pub Dt:
05/31/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONNECTION SUPPORTS AND METHOD OF MANUFACTURE THEREOF
33
Patent #:
Issue Dt:
11/05/2013
Application #:
12960178
Filing Dt:
12/03/2010
Publication #:
Pub Dt:
10/24/2013
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUMP-ON-LEAD INTERCONNECTION
34
Patent #:
Issue Dt:
01/08/2013
Application #:
12961202
Filing Dt:
12/06/2010
Publication #:
Pub Dt:
03/31/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER ON CONDUCTIVE TRACES FOR ELECTRICAL ISOLATION IN FINE PITCH BONDING
35
Patent #:
Issue Dt:
04/09/2013
Application #:
12961494
Filing Dt:
12/06/2010
Publication #:
Pub Dt:
07/14/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD INTERLOCKING MECHANISMS AND METHOD OF MANUFACTURE THEREOF
36
Patent #:
Issue Dt:
01/08/2013
Application #:
12963934
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
05/26/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ELECTRICAL INTERCONNECT WITH STRESS RELIEF VOID
37
Patent #:
Issue Dt:
10/01/2013
Application #:
12964577
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
06/14/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIELECTRIC SUPPORT AND METHOD OF MANUFACTURE THEREOF
38
Patent #:
Issue Dt:
08/06/2013
Application #:
12964617
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
06/14/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF
39
Patent #:
Issue Dt:
02/05/2013
Application #:
12964644
Filing Dt:
12/09/2010
Publication #:
Pub Dt:
04/07/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES AND METHOD FOR MANUFACTURING THEREOF
40
Patent #:
Issue Dt:
05/21/2013
Application #:
12964810
Filing Dt:
12/10/2010
Publication #:
Pub Dt:
06/14/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INDUCTOR WITHIN INTERCONNECT LAYER VERTICALLY SEPARATED FROM SEMICONDUCTOR DIE
41
Patent #:
Issue Dt:
02/19/2013
Application #:
12968266
Filing Dt:
12/14/2010
Publication #:
Pub Dt:
06/14/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPLE ROW LEADS AND METHOD OF MANUFACTURE THEREOF
42
Patent #:
Issue Dt:
02/26/2013
Application #:
12974265
Filing Dt:
12/21/2010
Publication #:
Pub Dt:
04/14/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION AND METHOD FOR MANUFACTURING THEREOF
43
Patent #:
Issue Dt:
03/26/2013
Application #:
13006697
Filing Dt:
01/14/2011
Publication #:
Pub Dt:
05/12/2011
Title:
SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBLE SPACER AND METHOD OF MANUFACTURE THEREOF
44
Patent #:
Issue Dt:
08/06/2013
Application #:
13017170
Filing Dt:
01/31/2011
Publication #:
Pub Dt:
05/19/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION AND METHOD FOR MANUFACTURING THEREOF
45
Patent #:
Issue Dt:
04/16/2013
Application #:
13023244
Filing Dt:
02/08/2011
Publication #:
Pub Dt:
05/26/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP
46
Patent #:
Issue Dt:
02/04/2014
Application #:
13031546
Filing Dt:
02/21/2011
Publication #:
Pub Dt:
08/23/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MULTI-LAYERED UBM WITH INTERMEDIATE INSULATING BUFFER LAYER TO REDUCE STRESS FOR SEMICONDUCTOR WAFER
47
Patent #:
Issue Dt:
09/17/2013
Application #:
13045523
Filing Dt:
03/10/2011
Publication #:
Pub Dt:
09/13/2012
Title:
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH UNDERFILLING STRUCTURES AND METHOD OF MANUFACTURE THEREOF
48
Patent #:
Issue Dt:
07/09/2013
Application #:
13048859
Filing Dt:
03/15/2011
Publication #:
Pub Dt:
09/20/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME STACKING MODULE AND METHOD OF MANUFACTURE THEREOF
49
Patent #:
Issue Dt:
01/21/2014
Application #:
13052590
Filing Dt:
03/21/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STEP MOLD AND METHOD OF MANUFACTURE THEREOF
50
Patent #:
Issue Dt:
04/30/2013
Application #:
13053096
Filing Dt:
03/21/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
51
Patent #:
Issue Dt:
12/17/2013
Application #:
13053142
Filing Dt:
03/21/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
52
Patent #:
Issue Dt:
04/02/2013
Application #:
13053719
Filing Dt:
03/22/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
53
Patent #:
Issue Dt:
11/13/2012
Application #:
13070219
Filing Dt:
03/23/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CONDUCTIVE STRUCTURE AND METHOD OF MANUFACTURE THEREOF
54
Patent #:
Issue Dt:
04/16/2013
Application #:
13070291
Filing Dt:
03/23/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIPCHIP LEADFRAME AND METHOD OF MANUFACTURE THEREOF
55
Patent #:
Issue Dt:
06/18/2013
Application #:
13070789
Filing Dt:
03/24/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF MANUFACTURE THEREOF
56
Patent #:
Issue Dt:
04/09/2013
Application #:
13070899
Filing Dt:
03/24/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME ETCHING AND METHOD OF MANUFACTURE THEREOF
57
Patent #:
Issue Dt:
10/29/2013
Application #:
13071397
Filing Dt:
03/24/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COLLAPSED MULTI-INTEGRATION PACKAGE AND METHOD OF MANUFACTURE THEREOF
58
Patent #:
Issue Dt:
12/10/2013
Application #:
13071433
Filing Dt:
03/24/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LOCKING INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
59
Patent #:
Issue Dt:
04/16/2013
Application #:
13071449
Filing Dt:
03/24/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF
60
Patent #:
Issue Dt:
10/15/2013
Application #:
13071514
Filing Dt:
03/25/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
61
Patent #:
Issue Dt:
03/19/2013
Application #:
13071760
Filing Dt:
03/25/2011
Publication #:
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
62
Patent #:
Issue Dt:
07/23/2013
Application #:
13081011
Filing Dt:
04/06/2011
Publication #:
Pub Dt:
07/28/2011
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT AND METHOD FOR MANUFACTURING THEREOF
63
Patent #:
Issue Dt:
11/27/2012
Application #:
13081227
Filing Dt:
04/06/2011
Publication #:
Pub Dt:
09/15/2011
Title:
METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS
64
Patent #:
Issue Dt:
12/18/2012
Application #:
13095680
Filing Dt:
04/27/2011
Publication #:
Pub Dt:
08/18/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
65
Patent #:
Issue Dt:
07/02/2013
Application #:
13100235
Filing Dt:
05/03/2011
Publication #:
Pub Dt:
11/08/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING COVER TO SEMICONDUCTOR DIE AND INTERPOSER WITH ADHESIVE MATERIAL
66
Patent #:
Issue Dt:
10/15/2013
Application #:
13102041
Filing Dt:
05/05/2011
Publication #:
Pub Dt:
11/08/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF
67
Patent #:
Issue Dt:
01/21/2014
Application #:
13105814
Filing Dt:
05/11/2011
Publication #:
Pub Dt:
11/15/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
68
Patent #:
Issue Dt:
07/09/2013
Application #:
13112717
Filing Dt:
05/20/2011
Publication #:
Pub Dt:
09/08/2011
Title:
THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS AND METHOD OF MANUFACTURE THEREOF
69
Patent #:
Issue Dt:
12/31/2013
Application #:
13118214
Filing Dt:
05/27/2011
Publication #:
Pub Dt:
11/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF
70
Patent #:
Issue Dt:
07/02/2013
Application #:
13118310
Filing Dt:
05/27/2011
Publication #:
Pub Dt:
11/29/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
71
Patent #:
Issue Dt:
03/05/2013
Application #:
13118955
Filing Dt:
05/31/2011
Publication #:
Pub Dt:
12/06/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
72
Patent #:
Issue Dt:
04/02/2013
Application #:
13149669
Filing Dt:
05/31/2011
Publication #:
Pub Dt:
12/06/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
73
Patent #:
Issue Dt:
11/19/2013
Application #:
13154308
Filing Dt:
06/06/2011
Publication #:
Pub Dt:
09/29/2011
Title:
INTEGRATED CIRCUIT PROTRUDING PAD PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
74
Patent #:
Issue Dt:
08/06/2013
Application #:
13159095
Filing Dt:
06/13/2011
Publication #:
Pub Dt:
10/06/2011
Title:
METHOD FOR MANUFACTURE OF INLINE INTEGRATED CIRCUIT SYSTEM
75
Patent #:
Issue Dt:
04/09/2013
Application #:
13160799
Filing Dt:
06/15/2011
Publication #:
Pub Dt:
10/06/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ISOLATION BARRIER AND METHOD FOR MANUFACTURING THEREOF
76
Patent #:
Issue Dt:
02/19/2013
Application #:
13161008
Filing Dt:
06/15/2011
Publication #:
Pub Dt:
10/06/2011
Title:
METHOD FOR MANUFACTURING WAFER SCALE HEAT SLUG SYSTEM
77
Patent #:
Issue Dt:
04/02/2013
Application #:
13161368
Filing Dt:
06/15/2011
Publication #:
Pub Dt:
12/20/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
78
Patent #:
Issue Dt:
07/02/2013
Application #:
13162513
Filing Dt:
06/16/2011
Publication #:
Pub Dt:
12/20/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTRA SUBSTRATE DIE AND METHOD OF MANUFACTURE THEREOF
79
Patent #:
Issue Dt:
09/10/2013
Application #:
13162526
Filing Dt:
06/16/2011
Publication #:
Pub Dt:
12/20/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE ON PACKAGE SUPPORT AND METHOD OF MANUFACTURE THEREOF
80
Patent #:
Issue Dt:
01/21/2014
Application #:
13163643
Filing Dt:
06/17/2011
Publication #:
Pub Dt:
12/20/2012
Title:
METHOD OF MANUFACTURING INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE
81
Patent #:
Issue Dt:
07/23/2013
Application #:
13164015
Filing Dt:
06/20/2011
Publication #:
Pub Dt:
07/26/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS
82
Patent #:
Issue Dt:
02/04/2014
Application #:
13164114
Filing Dt:
06/20/2011
Publication #:
Pub Dt:
12/20/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF
83
Patent #:
Issue Dt:
12/18/2012
Application #:
13169387
Filing Dt:
06/27/2011
Publication #:
Pub Dt:
10/20/2011
Title:
PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
84
Patent #:
Issue Dt:
01/15/2013
Application #:
13174033
Filing Dt:
06/30/2011
Publication #:
Pub Dt:
10/20/2011
Title:
Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant
85
Patent #:
Issue Dt:
09/10/2013
Application #:
13178347
Filing Dt:
07/07/2011
Publication #:
Pub Dt:
10/27/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONTOURED ENCAPSULATION AND METHOD FOR MANUFACTURING THEREOF
86
Patent #:
Issue Dt:
08/06/2013
Application #:
13181290
Filing Dt:
07/12/2011
Publication #:
Pub Dt:
01/26/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RDL WIDER THAN CONTACT PAD ALONG FIRST AXIS AND NARROWER THAN CONTACT PAD ALONG SECOND AXIS
87
Patent #:
Issue Dt:
08/06/2013
Application #:
13185384
Filing Dt:
07/18/2011
Publication #:
Pub Dt:
03/01/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADHESIVE MATERIAL OVER SEMICONDUCTOR DIE AND CARRIER TO REDUCE DIE SHIFTING DURING ENCAPSULATION
88
Patent #:
Issue Dt:
08/27/2013
Application #:
13194874
Filing Dt:
07/29/2011
Publication #:
Pub Dt:
11/24/2011
Title:
SEMICONDUCTOR SYSTEM WITH FINE PITCH LEAD FINGERS AND METHOD OF MANUFACTURING THEREOF
89
Patent #:
Issue Dt:
01/21/2014
Application #:
13196279
Filing Dt:
08/02/2011
Publication #:
Pub Dt:
11/24/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LAMINATE BASE
90
Patent #:
Issue Dt:
03/05/2013
Application #:
13197122
Filing Dt:
08/03/2011
Publication #:
Pub Dt:
11/24/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISOLATED PADS AND METHOD OF MANUFACTURE THEREOF
91
Patent #:
Issue Dt:
01/08/2013
Application #:
13209620
Filing Dt:
08/15/2011
Publication #:
Pub Dt:
12/08/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AFTER ENCAPSULATION AND GROUNDED THROUGH INTERCONNECT STRUCTURE
92
Patent #:
Issue Dt:
02/05/2013
Application #:
13211698
Filing Dt:
08/17/2011
Publication #:
Pub Dt:
12/08/2011
Title:
SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
93
Patent #:
Issue Dt:
04/09/2013
Application #:
13215131
Filing Dt:
08/22/2011
Publication #:
Pub Dt:
12/08/2011
Title:
NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE GROUND SITES
94
Patent #:
Issue Dt:
02/05/2013
Application #:
13223478
Filing Dt:
09/01/2011
Publication #:
Pub Dt:
12/22/2011
Title:
Semiconductor Device and Method of Forming Dam Material Around Periphery of Die to Reduce Warpage
95
Patent #:
Issue Dt:
10/22/2013
Application #:
13224718
Filing Dt:
09/02/2011
Publication #:
Pub Dt:
03/07/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED THERMAL HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF
96
Patent #:
Issue Dt:
07/23/2013
Application #:
13224725
Filing Dt:
09/02/2011
Publication #:
Pub Dt:
03/07/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STIFFENER AND METHOD OF MANUFACTURE THEREOF
97
Patent #:
Issue Dt:
08/06/2013
Application #:
13228226
Filing Dt:
09/08/2011
Publication #:
Pub Dt:
01/26/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF CONFORMING CONDUCTIVE VIAS BETWEEN INSULATING LAYERS IN SAW STREETS
98
Patent #:
Issue Dt:
08/06/2013
Application #:
13228248
Filing Dt:
09/08/2011
Publication #:
Pub Dt:
01/26/2012
Title:
SEMICONDUCTOR DEVICE WITH CONDUCTIVE VIAS BETWEEN SAW STREETS
99
Patent #:
Issue Dt:
08/20/2013
Application #:
13235135
Filing Dt:
09/16/2011
Publication #:
Pub Dt:
03/21/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE UNDERLAYER AND METHOD OF MANUFACTURE THEREOF
100
Patent #:
Issue Dt:
12/10/2013
Application #:
13235202
Filing Dt:
09/16/2011
Publication #:
Pub Dt:
03/21/2013
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDE MOLD AND METHOD OF MANUFACTURE THEREOF
Assignor
1
Exec Dt:
05/03/2019
Assignees
1
46429 LANDING PARKWAY
FREMONT, CALIFORNIA 94538
2
5 YISHUN STREET 23
SINGAPORE, SINGAPORE 768442
Correspondence name and address
PATENT LAW GROUP: ATKINS AND ASSOCIATES
123 W. CHANDLER HEIGHTS ROAD, #12535
CHANDLER, AZ 85248

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