|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10287612
|
Filing Dt:
|
11/04/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2004
| | | | |
|
Title:
|
STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10289020
|
Filing Dt:
|
11/05/2002
|
|
Title:
|
METHOD AND STRUCTURE FOR DETERMINING A CONCENTRATION PROFILE OF AN IMPURITY WITHIN A SEMICONDUCTOR LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
10291293
|
Filing Dt:
|
11/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
METHOD OF FORMING FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10299429
|
Filing Dt:
|
11/18/2002
|
|
Title:
|
METHOD AND APPARATUS FOR ATTACHING USB PERIPHERALS TO HOST PORTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10301768
|
Filing Dt:
|
11/20/2002
|
|
Title:
|
METHOD AND APPARATUS FOR CONVERGING A CONTROL LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10304762
|
Filing Dt:
|
11/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10305625
|
Filing Dt:
|
11/27/2002
|
|
Title:
|
CURRENT STEERING REDUCED BITLINE VOLTAGE SWING, SENSE AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2003
|
Application #:
|
10305699
|
Filing Dt:
|
11/26/2002
|
|
Title:
|
PARALLEL TEST IN ASYNCHRONOUS MEMORY WITH SINGLE-ENDED OUTPUT PATH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10305724
|
Filing Dt:
|
11/26/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
LATERAL DOPED CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
10306381
|
Filing Dt:
|
11/27/2002
|
|
Title:
|
CLASS AB ANALOG INVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10306414
|
Filing Dt:
|
11/27/2002
|
|
Title:
|
PROCESSES PROVIDING HIGH AND LOW THRESHOLD P-TYPE AND N-TYPE TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10309664
|
Filing Dt:
|
12/03/2002
|
|
Title:
|
BOUNDARY SCAN REGISTER FOR DIFFERENTIAL CHIP CORE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
|
Application #:
|
10313048
|
Filing Dt:
|
12/06/2002
|
|
Title:
|
SELECTIVE OXIDATION OF GATE STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10313049
|
Filing Dt:
|
12/06/2002
|
|
Title:
|
NITRIDE SPACER FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2004
|
Application #:
|
10313267
|
Filing Dt:
|
12/06/2002
|
|
Title:
|
CONTROLLED THICKNESS GATE STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
10314060
|
Filing Dt:
|
12/05/2002
|
|
Title:
|
METHOD OF FORMING COPPER SULFIDE FOR MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10314380
|
Filing Dt:
|
12/06/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
|
Title:
|
MULTI-LAYER GATE STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10314591
|
Filing Dt:
|
12/09/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
|
Title:
|
SELF ALIGNED MEMORY ELEMENT AND WORDLINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2004
|
Application #:
|
10319318
|
Filing Dt:
|
12/13/2002
|
|
Title:
|
METHOD FOR PLASMA ETCHING A MICROELECTRONIC TOPOGRAPHY USING A PULSE BIAS POWER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10320012
|
Filing Dt:
|
12/16/2002
|
|
Title:
|
LOT-TO-LOT FEED FORWARD CMP PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10320910
|
Filing Dt:
|
12/17/2002
|
|
Title:
|
DIFFERENTIALLY MIS-ALIGNED CONTACTS IN FLASH ARRAYS TO CALIBRATE FAILURE MODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10321965
|
Filing Dt:
|
12/17/2002
|
|
Title:
|
SEMICONDUCTOR STRUCTURE HAVING ALIGNMENT MARKS WITH SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10323002
|
Filing Dt:
|
12/18/2002
|
|
Title:
|
FABRICATION OF A BIPOLAR TRANSISTOR USING A SACRIFICIAL EMITTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10324308
|
Filing Dt:
|
12/18/2002
|
|
Title:
|
METHOD AND APPARATUS FOR RE-ACCESSING A FIFO LOCATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10324455
|
Filing Dt:
|
12/20/2002
|
|
Title:
|
PROGRAMMABLE OSCILLATOR SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10325008
|
Filing Dt:
|
12/20/2002
|
|
Title:
|
MAGNETIC MEMORY ARRAY WITH AN IMPROVED WORD LINE CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
10325011
|
Filing Dt:
|
12/20/2002
|
|
Title:
|
APPARATUS, SYSTEM, AND METHOD FOR SYNCHRONIZING SIGNALS RECEIVED BY ONE OR MORE SYSTEM COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
10325204
|
Filing Dt:
|
12/18/2002
|
|
Title:
|
METHOD AND SYSTEM FOR PROTECTING A WIRELESS NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10326525
|
Filing Dt:
|
12/20/2002
|
|
Title:
|
SELF-ALIGNED CONTACT STRUCTURE WITH RAISED SOURCE AND DRAIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10326707
|
Filing Dt:
|
12/20/2002
|
|
Title:
|
FORMATION OF A SHALLOW TRENCH ISOLATION STRUCTURE IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2004
|
Application #:
|
10327217
|
Filing Dt:
|
12/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
SINGLE ENDED CLOCK SIGNAL GENERATOR HAVING A DIFFERENTIAL OUTPUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10327571
|
Filing Dt:
|
12/20/2002
|
|
Title:
|
REDUCING CROWBAR CURRENT IN A LATCH HYSTERESIS RECEIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10328265
|
Filing Dt:
|
12/23/2002
|
|
Title:
|
METHOD OF PROTECTING FLASH MEMORY FROM DATA CORRUPTION DURING FAST POWER DOWN EVENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10328904
|
Filing Dt:
|
12/23/2002
|
|
Title:
|
ANALOG SPREAD SPECTRUM SIGNAL GENERATION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
10329162
|
Filing Dt:
|
12/24/2002
|
|
Title:
|
ANALOG I/O WITH DIGITAL SIGNAL PROCESSOR ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10330589
|
Filing Dt:
|
12/27/2002
|
|
Title:
|
HIERARCHICALLY EXPANDABLE FAIR ARBITER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10338333
|
Filing Dt:
|
01/07/2003
|
|
Title:
|
SYSTEM AND METHOD FOR CHARGE RESTORATION IN A NON-VOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10339115
|
Filing Dt:
|
01/09/2003
|
|
Title:
|
CIRCUIT FOR LOCKING AN OSCILLATOR TO A DATA STREAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
|
10339536
|
Filing Dt:
|
01/08/2003
|
|
Title:
|
METHOD AND SYSTEM FOR TESTING TUNNEL OXIDE ON A MEMORY-RELATED STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10342032
|
Filing Dt:
|
01/14/2003
|
|
Title:
|
FLASH MEMORY DEVICES WITH OXYNITRIDE DIELECTRIC AS THE CHARGE STORAGE MEDIA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10349106
|
Filing Dt:
|
01/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2003
| | | | |
|
Title:
|
DC OFFSET CANCEL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2004
|
Application #:
|
10349107
|
Filing Dt:
|
01/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/14/2003
| | | | |
|
Title:
|
DC OFFSET CANCEL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10353553
|
Filing Dt:
|
01/29/2003
|
|
Title:
|
METHOD OF ADJUSTING THE THRESHOLD VOLTAGE OF A MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10356449
|
Filing Dt:
|
01/31/2003
|
|
Title:
|
METHOD AND DEVICE FOR GENERATING FREQUENCY ADJUSTMENT PARAMETERS FOR A VOLTAGE CONTROLLED OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10358589
|
Filing Dt:
|
02/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10359872
|
Filing Dt:
|
02/07/2003
|
|
Title:
|
METHOD OF FORMATION OF SEMICONDUCTOR RESISTANT TO HOT CARRIER INJECTION STRESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10361455
|
Filing Dt:
|
02/10/2003
|
|
Title:
|
METHOD FOR FABRICATING DEVICES IN CORE AND PERIPHERY SEMICONDUCTOR REGIONS USING DUAL SPACERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10364569
|
Filing Dt:
|
02/10/2003
|
|
Title:
|
STRUCTURE AND METHOD FOR SUPPRESSING OXIDE ENCROACHMENT IN A FLOATING GATE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2004
|
Application #:
|
10364756
|
Filing Dt:
|
02/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/10/2003
| | | | |
|
Title:
|
PC CARD RETRACTABLE ANTENNA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2004
|
Application #:
|
10375534
|
Filing Dt:
|
02/27/2003
|
|
Title:
|
SEMICONDUCTOR TOPOGRAPHY HAVING AN INACTIVE REGION FORMED FROM A DUMMY STRUCTURE PATTERN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2005
|
Application #:
|
10378885
|
Filing Dt:
|
03/05/2003
|
|
Title:
|
IMPLANT DAMAGE REMOVAL BY LASER THERMAL ANNEALING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10384856
|
Filing Dt:
|
03/10/2003
|
|
Title:
|
METHOD AND SYSTEM FOR APPLYING TESTING VOLTAGE SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10384936
|
Filing Dt:
|
03/10/2003
|
|
Title:
|
METHOD AND SYSTEM FOR DETECTING DEFECTIVE MATERIAL SURROUNDING FLASH MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10387774
|
Filing Dt:
|
03/12/2003
|
|
Title:
|
MEMORY DEVICE HAVING REVERSE LDD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
10389149
|
Filing Dt:
|
03/13/2003
|
|
Title:
|
APPARATUS AND METHOD FOR A SENSE AMPLIFIER CIRCUIT THAT SAMPLES AND HOLDS A REFERENCE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
10393032
|
Filing Dt:
|
03/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
|
Title:
|
ADJUSTMENT OF THRESHOLD VOLTAGES OF SELECTED NMOS AND PMOS TRANSISTORS USING FEWER MASKING STEPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10396005
|
Filing Dt:
|
03/25/2003
|
|
Title:
|
PHASE-FREQUENCY DETECTOR AND CHARGE PUMP WITH FEEDBACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2005
|
Application #:
|
10402750
|
Filing Dt:
|
03/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
|
Title:
|
GATE ELECTRODE FOR MOS TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10404081
|
Filing Dt:
|
04/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2003
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE LOW TEMPERATURE TEST APPARATUS USING ELECTRONIC COOLING ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10405272
|
Filing Dt:
|
04/02/2003
|
|
Title:
|
PHOTOSENSITIVE POLYMERIC MEMORY ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10406130
|
Filing Dt:
|
04/03/2003
|
|
Title:
|
BMC-HOSTED REAL-TIME CLOCK AND NON-VOLATILE RAM REPLACEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10407999
|
Filing Dt:
|
04/03/2003
|
|
Title:
|
MEMORY DEVICE HAVING IMPROVED PERIPHERY AND CORE ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
10418197
|
Filing Dt:
|
04/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2003
| | | | |
|
Title:
|
DIFFERENTIAL CIRCUIT AND PEAK HOLD CIRCUIT INCLUDING DIFFERENTIAL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10419206
|
Filing Dt:
|
04/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2003
| | | | |
|
Title:
|
FREQUENCY SYNTHESIZER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
10430582
|
Filing Dt:
|
05/06/2003
|
|
Title:
|
TRENCH SIDE WALL CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10430604
|
Filing Dt:
|
05/06/2003
|
|
Title:
|
MEMORY DEVICE WITH REDUCED OPERATING VOLTAGE HAVING DIELECTRIC STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
10430991
|
Filing Dt:
|
05/07/2003
|
|
Title:
|
METHOD AND APPARATUS FOR ACCURATELY READING A POTENTIOMETER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
10431322
|
Filing Dt:
|
05/06/2003
|
|
Title:
|
METHOD AND SYSTEM FOR IMPROVING SHORT CHANNEL EFFECT ON A FLOATING GATE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
10436411
|
Filing Dt:
|
05/12/2003
|
|
Title:
|
ISOLATION TECHNOLOGY FOR SUBMICRON SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2005
|
Application #:
|
10436786
|
Filing Dt:
|
05/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/18/2004
| | | | |
|
Title:
|
ERASING AND PROGRAMMING AN ORGANIC MEMORY DEVICE AND METHOD OF FABRICATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10438942
|
Filing Dt:
|
05/16/2003
|
|
Title:
|
LASER THERMAL ANNEALING METHODS FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
10452877
|
Filing Dt:
|
06/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
PLANAR POLYMER MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10614066
|
Filing Dt:
|
07/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE FOR DIFFERENTIAL DATA AMPLIFICATION AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10614177
|
Filing Dt:
|
07/08/2003
|
|
Title:
|
FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10614484
|
Filing Dt:
|
07/07/2003
|
|
Title:
|
SILICON CONTAINING MATERIAL FOR PATTERNING POLYMERIC MEMORY ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10616804
|
Filing Dt:
|
07/09/2003
|
|
Title:
|
METHOD FOR FABRICATING A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10617451
|
Filing Dt:
|
07/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
PECVD SILICON-RICH OXIDE LAYER FOR REDUCED UV CHARGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10618156
|
Filing Dt:
|
07/11/2003
|
|
Title:
|
MEMORY STRUCTURE HAVING TUNABLE INTERLAYER DIELECTRIC AND METHOD FOR FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10618191
|
Filing Dt:
|
07/10/2003
|
|
Title:
|
FLASH MEMORY CELL HAVING REDUCED LEAKAGE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10631199
|
Filing Dt:
|
07/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10631856
|
Filing Dt:
|
08/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE SUPPLYING PROPER PROGRAM POTENTIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10634857
|
Filing Dt:
|
08/06/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/26/2004
| | | | |
|
Title:
|
DESIGN METHOD FOR INTEGRATED CIRCUIT HAVING SCAN FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10649672
|
Filing Dt:
|
08/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
|
Title:
|
PLL CLOCK GENERATOR CIRCUIT AND CLOCK GENERATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10655179
|
Filing Dt:
|
09/04/2003
|
|
Title:
|
MEMORY CELL STRUCTURE HAVING NITRIDE LAYER WITH REDUCED CHARGE LOSS AND METHOD FOR FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10655936
|
Filing Dt:
|
09/04/2003
|
|
Title:
|
METHOD OF FABRICATING A FLOATING GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2008
|
Application #:
|
10658936
|
Filing Dt:
|
09/09/2003
|
|
Title:
|
FLASH MEMORY WITH HIGH-K DIELECTRIC MATERIAL BETWEEN SUBSTRATE AND GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
10658937
|
Filing Dt:
|
09/09/2003
|
|
Title:
|
METHOD AND APPARATUS FOR COUPLING TO A SOURCE LINE IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10660420
|
Filing Dt:
|
09/10/2003
|
|
Title:
|
HIGH DENSITY FLOATING GATE FLASH MEMORY AND FABRICATION PROCESSES THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10662011
|
Filing Dt:
|
09/11/2003
|
|
Title:
|
METHOD FOR FABRICATING A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10662636
|
Filing Dt:
|
09/15/2003
|
|
Title:
|
FORMING A SUBSTANTIALLY PLANAR UPPER SURFACE AT THE OUTER EDGE OF A SEMICONDUCTOR TOPOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10665205
|
Filing Dt:
|
09/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
CONTROL METHOD OF NON-VOLATILE SEMICONDUCTOR MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10676612
|
Filing Dt:
|
10/01/2003
|
|
Title:
|
ORGANIC MEMORY CELL FORMATION ON AG SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10677042
|
Filing Dt:
|
10/01/2003
|
|
Title:
|
SELF ASSEMBLY OF CONDUCTING POLYMER FOR FORMATION OF POLYMER MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10681306
|
Filing Dt:
|
10/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2004
| | | | |
|
Title:
|
CURRENT PULSE RECEIVING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10683631
|
Filing Dt:
|
10/10/2003
|
|
Title:
|
RECESSED CHANNEL
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10689034
|
Filing Dt:
|
10/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
Method of making metallization and contact structures in an integrated circuit using a timed trench etch
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10696234
|
Filing Dt:
|
10/28/2003
|
|
Title:
|
METHOD FOR FORMING A DIELECTRIC SPACER IN A NON-VOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10699155
|
Filing Dt:
|
10/31/2003
|
|
Title:
|
MAGNETIC MEMORY ARRAY CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10700021
|
Filing Dt:
|
11/03/2003
|
|
Title:
|
MEMORY ELEMENT FORMATION WITH PHOTOSENSITIVE POLYMER DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10706664
|
Filing Dt:
|
11/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
|
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT
|
|
