|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09128864
|
Filing Dt:
|
08/04/1998
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2001
| | | | |
|
Title:
|
HIGH DENSITY MEMORY CELL ASSEMBLY AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09128901
|
Filing Dt:
|
08/04/1998
|
|
Title:
|
DIFFERENTIAL CHARGE PUMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09131778
|
Filing Dt:
|
08/10/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A BOOST CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
09132100
|
Filing Dt:
|
08/10/1998
|
|
Title:
|
METHOD, ARCHITECTURE AND CIRCUIT FOR REDUCING AND/OR ELIMINATING SMALL SIGNAL VOLTAGE SWING SENSITIVITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
09132347
|
Filing Dt:
|
08/12/1998
|
|
Title:
|
METHOD FOR SENSING STATE OF ERASURE OF A FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
09132981
|
Filing Dt:
|
08/12/1998
|
|
Title:
|
METHOD FOR TIGHTENING ERASE THRESHOLD VOLTAGE DISTRIBUTION IN FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09134525
|
Filing Dt:
|
08/14/1998
|
|
Title:
|
MULTIPURPOSE GRADED SILICON OXYNITRIDE CAP LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09134526
|
Filing Dt:
|
08/14/1998
|
|
Title:
|
METHOD FOR FABRICATING A DOPED POLYSILICON FEATURE IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2000
|
Application #:
|
09137914
|
Filing Dt:
|
08/20/1998
|
|
Title:
|
NON-VOLATILE, STATIC RANDOM ACCESS MEMORY WITH STORE DISTURB IMMUNITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
09143090
|
Filing Dt:
|
08/28/1998
|
|
Title:
|
METHODS AND ARRANGEMENTS FOR INTRODUCING NITROGEN INTO A TUNNEL OXIDE IN A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09143899
|
Filing Dt:
|
08/31/1998
|
|
Title:
|
METHOD FOR FORMING AN INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
09144353
|
Filing Dt:
|
08/31/1998
|
|
Title:
|
METHOD FOR CLEANING A SURFACE OF A DIELECTRIC MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09144506
|
Filing Dt:
|
08/31/1998
|
|
Title:
|
SCALABLE AND RELIABLE INTEGRATED CIRCUIT INTER-LEVEL DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09144521
|
Filing Dt:
|
08/31/1998
|
|
Title:
|
REDUCTION OF SILICON OXYNITRIDE FILM DELAMINATION IN INTEGRATED CIRCUIT INTER-LEVEL DIELECTRICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09146032
|
Filing Dt:
|
09/02/1998
|
|
Title:
|
METHOD FOR MANUFACTURING MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09150551
|
Filing Dt:
|
09/09/1998
|
|
Title:
|
SELF-TIMED SYNCHRONOUS PULSE GENERATOR WITH TEST MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09153941
|
Filing Dt:
|
09/16/1998
|
|
Title:
|
PROGRAMMABLE BUS HOLD CIRCUIT AND METHOD OF USING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09154072
|
Filing Dt:
|
09/16/1998
|
|
Title:
|
STACKED GATE STRUCTURE FOR FLASH MEMORY APPLICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
09154073
|
Filing Dt:
|
09/16/1998
|
|
Title:
|
METAL OXIDE STACK FOR FLASH MEMORY APPLICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
09154074
|
Filing Dt:
|
09/16/1998
|
|
Title:
|
METHODS FOR FORMING NITROGEN-RICH REGIONS IN A FLOATING GATE AND INTERPOLY DIELECTRIC LAYER IN A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
09159023
|
Filing Dt:
|
09/23/1998
|
|
Title:
|
METHOD OF MAKING FLEXIBLY PARTITIONED METAL LINE SEGMENTS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
09159342
|
Filing Dt:
|
09/23/1998
|
|
Title:
|
MEMORY ADDRESS DECODING CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09159908
|
Filing Dt:
|
09/24/1998
|
|
Title:
|
CIRCUITS, ARCHITECTURES AND METHODS FOR DETECTING AND CORRECTING EXCESS OSCILLATOR FREQUENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
09160046
|
Filing Dt:
|
09/25/1998
|
|
Publication #:
|
|
Pub Dt:
|
09/06/2001
| | | | |
|
Title:
|
FLASH MEMORY DEVICE AND A FABRICATION PROCESS THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
09160858
|
Filing Dt:
|
09/25/1998
|
|
Title:
|
SECONDARY STORAGE DEVICE USING NONVOLATILE SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
09161423
|
Filing Dt:
|
09/24/1998
|
|
Title:
|
METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09161821
|
Filing Dt:
|
09/28/1998
|
|
Title:
|
CONFIGURABLE CLOCK GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09162107
|
Filing Dt:
|
09/28/1998
|
|
Title:
|
HIGH DENSITY LEAD FRAMES AND METHODS FOR PLASTIC INJECTION MOLDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09163310
|
Filing Dt:
|
09/30/1998
|
|
Title:
|
SELF-ALIGNING POLY 1 ONO DIELECTRIC FOR NON-VOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09163315
|
Filing Dt:
|
09/30/1998
|
|
Title:
|
VIABLE MEMORY CELL FORMED USING RAPID THERMAL ANNEALING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09164531
|
Filing Dt:
|
09/30/1998
|
|
Title:
|
NON-VOLATILE, STATIC RANDOM ACCESS MEMORY WITH HIGH SPEED STORE CAPABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09164952
|
Filing Dt:
|
10/01/1998
|
|
Title:
|
HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCUIT MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09166384
|
Filing Dt:
|
10/05/1998
|
|
Title:
|
METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09166385
|
Filing Dt:
|
10/05/1998
|
|
Title:
|
WORDLINE DRIVER FOR FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09167799
|
Filing Dt:
|
10/07/1998
|
|
Title:
|
DYNAMIC SLEW RATE CONTROL OUTPUT BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09170061
|
Filing Dt:
|
10/13/1998
|
|
Title:
|
METHOD OF FORMING A COMPOSITE INTERPOLY GATE DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2000
|
Application #:
|
09172410
|
Filing Dt:
|
10/14/1998
|
|
Title:
|
FLASH MEMORY DEVICE HAVING HIGH PERMITTIVITY STACKED DIELECTRIC AND FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09172956
|
Filing Dt:
|
10/14/1998
|
|
Title:
|
DEVICE AND METHOD FOR INTERCONNECTING UNIVERSAL SERIAL BUSES INCLUDING POWER MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09173470
|
Filing Dt:
|
10/14/1998
|
|
Title:
|
DEVICE AND METHOD FOR SYNCHRONIZING THE CLOCKS OF INTERCONNECTED UNIVERSAL SERIAL BUSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09176047
|
Filing Dt:
|
10/20/1998
|
|
Title:
|
DEVICE AND METHOD FOR EFFICIENT BULK DATA RETRIEVAL USING A UNIVERSAL SERIAL BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09177294
|
Filing Dt:
|
10/22/1998
|
|
Title:
|
PROCESS FOR FABRICATING A COMMON SOURCE REGION IN MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09177392
|
Filing Dt:
|
10/23/1998
|
|
Title:
|
METHOD OF MANUFACTURING FERROELECTRIC MEMORY DEVICE USEFUL FOR PREVENTING HYDROGEN LINE DEGRADATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09177817
|
Filing Dt:
|
10/23/1998
|
|
Title:
|
HIGH VOLTAGE TRANSISTOR WITH HIGH GATED DIODE BREAKDOWN VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09179280
|
Filing Dt:
|
10/26/1998
|
|
Title:
|
OVERVOLTAGE TOLERANT INTEGRATED CIRCUIT INPUT/OUTPUT INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09182525
|
Filing Dt:
|
10/30/1998
|
|
Title:
|
HIGH VOLTAGE TRANSISTOR WITH LOW BODY EFFECT AND LOW LEAKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
09189227
|
Filing Dt:
|
11/11/1998
|
|
Title:
|
LPCVD OXIDE AND RTA FOR TOP OXIDE OF ONO FILM TO IMPROVE RELIABILITY FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09192715
|
Filing Dt:
|
11/16/1998
|
|
Title:
|
SELECTABLE SINGLE ENDED-TO DIFFERENTIAL OUTPUT ADJUSTMENT SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09198654
|
Filing Dt:
|
11/24/1998
|
|
Title:
|
METHOD FOR FABRICATING A HIGH-DENSITY AND HIGH-RELIABILITY EEPROM DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09198747
|
Filing Dt:
|
11/24/1998
|
|
Title:
|
SEMICONDUCTOR REFERENCE VOLTAGE GENERATOR HAVING A NON VOLATILE MEMORY STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09199265
|
Filing Dt:
|
11/25/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE CONTAINING P-HDP INTERDIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09199772
|
Filing Dt:
|
11/25/1998
|
|
Title:
|
METHOD FOR IMPROVING ELECTROSTATIC DISCHARGE ( ESD) ROBUSTNESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09200219
|
Filing Dt:
|
11/25/1998
|
|
Title:
|
OUTPUT DATA PATH SCHEME IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09200373
|
Filing Dt:
|
11/24/1998
|
|
Title:
|
INTERRUPTIBLE STATE MACHINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09205558
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
UNIVERSAL SERIAL BUS PERIPHERAL BRIDGE SIMULATES A DEVICE DISCONNECT CONDITION TO A HOST WHEN THE DEVICE IS IN A NOT-READY CONDITION TO AVOID WASTING BUS RESOURCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09205899
|
Filing Dt:
|
12/04/1998
|
|
Title:
|
METHOD OF FORMING ONO STACKED FILMS AND DCS TUNGSTEN SILICIDE GATE TO IMPROVE POLYCIDE GATE PERFORMANCE FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
09207713
|
Filing Dt:
|
12/09/1998
|
|
Title:
|
METHOD FOR SHALLOW TRENCH ISOLATION AND SHALLOW TRENCH ISOLATION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09208889
|
Filing Dt:
|
12/10/1998
|
|
Title:
|
MULTIPORT MEMORY SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09216460
|
Filing Dt:
|
12/18/1998
|
|
Title:
|
CIRCUIT AND METHOD FOR CONTROLLING AN OUTPUT OF A RING OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2002
|
Application #:
|
09219663
|
Filing Dt:
|
12/23/1998
|
|
Title:
|
PROGRAMMABLE GATE ARRAY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09221989
|
Filing Dt:
|
12/29/1998
|
|
Title:
|
TRANSISTOR OUTPUT CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2001
|
Application #:
|
09222578
|
Filing Dt:
|
12/28/1998
|
|
Title:
|
SCHEME FOR REDUCING LEAKAGE CURRENT IN AN INPUT BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09223281
|
Filing Dt:
|
12/30/1998
|
|
Title:
|
NONVOLATILE SEMICONDUTOR MEMORY DEVICE AND METHOD OF REPRODUCING DATA OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
09226748
|
Filing Dt:
|
01/06/1999
|
|
Title:
|
ONE-PIN SHIFT REGISTER INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09231211
|
Filing Dt:
|
01/14/1999
|
|
Title:
|
SELF-ADJUSTING OPTIMAL DELAY TIME FILTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09232023
|
Filing Dt:
|
01/14/1999
|
|
Title:
|
EEPROM DECODER BLOCK HAVING A P-WELL COUPLED TO A CHARGE PUMP FOR CHARGING THE P-WELL AND METHOD OF PROGRAMMING WITH THE EEPROM DECODER BLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09232578
|
Filing Dt:
|
01/16/1999
|
|
Title:
|
DEDICATED CIRCUIT AND METHOD FOR ENUMERATING AND OPERATING A PERIPHERAL DEVICE ON A UNIVERSAL SERIAL BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
09238270
|
Filing Dt:
|
01/27/1999
|
|
Title:
|
CIRCUIT AND METHOD FOR IMPLEMENTING SINGLE-CYCLE READ/WRITE OPERATION(S), AND RANDOM ACCESS MEMORY INCLUDING THE CIRCUIT AND/OR PRACTICING THE METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09238953
|
Filing Dt:
|
01/27/1999
|
|
Title:
|
RANDOM ACCESS MEMORY HAVING INDEPENDENT READ PORT AND WRITE PORT AND PROCESS FOR WRITING TO AND READING FROM THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09238954
|
Filing Dt:
|
01/27/1999
|
|
Title:
|
RANDOM ACCESS MEMORY HAVING A READ/WRITE ADDRESS BUS AND PROCESS FOR WRITING TO AND READING FROM THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09241082
|
Filing Dt:
|
02/01/1999
|
|
Title:
|
SYSTEM LSI HAVING COMMUNICATION FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09244429
|
Filing Dt:
|
02/04/1999
|
|
Title:
|
SEMICONDUCTOR DEVICES WITH REDUCED CONTROL GATE DIMENSIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09246981
|
Filing Dt:
|
02/09/1999
|
|
Title:
|
CLOCK GENERATOR WITH PROGRAMMABLE TWO-TONE MODULATION FOR EMI REDUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
09247546
|
Filing Dt:
|
02/10/1999
|
|
Title:
|
MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09252123
|
Filing Dt:
|
02/18/1999
|
|
Title:
|
SCHEME FOR INCREASING ENMABLE ACCESS SPEED IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09252185
|
Filing Dt:
|
02/18/1999
|
|
Title:
|
LOW DIELECTRIC SEMICONDUCTOR DEVICE WITH RIGID, CONDUCTIVELY LINED INTERCONNECTION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09252854
|
Filing Dt:
|
09/08/1998
|
|
Title:
|
NOVEL PROCESS FOR RELIABLE ULTRATHIN OXYNITRIDE FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09253991
|
Filing Dt:
|
02/22/1999
|
|
Title:
|
SELECTIVE SAC ETCH PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2002
|
Application #:
|
09255108
|
Filing Dt:
|
02/22/1999
|
|
Title:
|
IN LINE YIELD PREDICTION USING ADC DETERMINED KILL RATIOS DIE HEALTH STATISTICS AND DIE STACKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09257468
|
Filing Dt:
|
02/24/1999
|
|
Title:
|
CONFIGURABLE MEMORY BLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09257733
|
Filing Dt:
|
02/25/1999
|
|
Title:
|
USE OF IMPLANTED IONS TO REDUCE OXIDE-NITRIDE-OXIDE (ONO) ETCH RESIDUE AND POLYSTRINGERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2001
|
Application #:
|
09259482
|
Filing Dt:
|
02/26/1999
|
|
Title:
|
HIGH RELIABILITY LEAD FRAME AND PACKAGING TECHNOLOGY CONTAINING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09262430
|
Filing Dt:
|
03/04/1999
|
|
Title:
|
LOW SUPPLY VOLTAGE BICMOS SELF-BIASED BANDGAP REFERENCE USING A CURRENT SUMMING ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2002
|
Application #:
|
09263699
|
Filing Dt:
|
03/05/1999
|
|
Title:
|
EFFECT OF DOPED AMORPHOUS SI THICKNESS ON BETTER POLY 1 CONTACT RESISTANCE PERFORMANCE FOR NAND TYPE FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
09263701
|
Filing Dt:
|
03/05/1999
|
|
Title:
|
METHOD TO ELIMATE SILICIDE CRACKING FOR NAND TYPE FLASH MEMORY DEVICES BY IMPLANTING A POLISH RATE IMPROVER INTO THE SECOND POLYSILICON LAYER AND POLISHING IT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09263983
|
Filing Dt:
|
03/05/1999
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
|
Title:
|
METHOD OF FORMING HIGH K TANTALUM PENTOXIDE TA205 INSTEAD OF ONO STACKED FILMS TO INCREASE COUPLING RATIO AND IMPROVE RELIABILITY FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2005
|
Application #:
|
09266869
|
Filing Dt:
|
03/12/1999
|
|
Title:
|
MICROCONTROLLER HAVING PREFETCH FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
09271330
|
Filing Dt:
|
03/18/1999
|
|
Title:
|
METHOD AND APPARATUS FOR PREVENTING P1 PUNCHTHROUGH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09273310
|
Filing Dt:
|
03/19/1999
|
|
Title:
|
UNIVERSAL SERIAL BUS PERIPHERAL BRIDGE WITH SEQUENCER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09275336
|
Filing Dt:
|
03/24/1999
|
|
Title:
|
PROGRAMMABLE OSCILLATOR SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09275373
|
Filing Dt:
|
03/24/1999
|
|
Title:
|
METHOD FOR REDUCING STATIC PHASE OFFSET IN A PLL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09276321
|
Filing Dt:
|
03/25/1999
|
|
Title:
|
VOLTAGE CONVERSION/ REGULATOR CIRCUIT AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09276947
|
Filing Dt:
|
03/26/1999
|
|
Title:
|
CHARGE PUMP ARCHITECTURE FOR INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09277616
|
Filing Dt:
|
03/26/1999
|
|
Title:
|
NONVOLATILE CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09281672
|
Filing Dt:
|
03/30/1999
|
|
Title:
|
METHOD FOR FORMING NITROGEN-RICH SILICON OXIDE-BASED DIELECTRIC MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09283166
|
Filing Dt:
|
04/01/1999
|
|
Title:
|
BARRIER LAYER TO PROTECT A FERROELECTRIC CAPACITOR AFTER CONTACT HAS BEEN MADE TO THE CAPACITOR ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09283308
|
Filing Dt:
|
03/31/1999
|
|
Title:
|
BARRIER LAYER DECREASES NITROGEN CONTAMINATION OF PERIPHERAL GATE REGIONS DURING TUNNEL OXIDE NITRIDATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
|
Application #:
|
09286464
|
Filing Dt:
|
04/06/1999
|
|
Title:
|
METHOD FOR TRIMMING A PHOTORESIST PATTERN LINE FOR MEMORY GATE ETCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09288376
|
Filing Dt:
|
04/08/1999
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
SYNCHRONIZATION MANAGER FOR STANDARDIZED SYNCHRONIZATION OF SEPARATE PROGRAMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09300817
|
Filing Dt:
|
04/27/1999
|
|
Title:
|
METHODS OF FILLING CONSTRAINED SPACES WITH INSULATING MATERIALS AND/OR OF FORMING CONTACT HOLES AND/OR CONTACTS IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2002
|
Application #:
|
09304519
|
Filing Dt:
|
05/04/1999
|
|
Title:
|
ELECTRIC DEVICE WITH FLASH MEMORY BUILT-IN
|
|
