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Reel/Frame:040911/0238   Pages: 159
Recorded: 12/14/2016
Attorney Dkt #:AUG-CSC-MRL
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1953
Page 5 of 20
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
Patent #:
6185124
Issue Dt:
02/06/2001
Application #:
09306306
Filing Dt:
05/06/1999
Title:
STORAGE CIRCUIT APPARATUS
2
Patent #:
6188609
Issue Dt:
02/13/2001
Application #:
09307259
Filing Dt:
05/06/1999
Title:
RAMPED OR STEPPED GATE CHANNEL ERASE FOR FLASH MEMORY APPLICATION
3
Patent #:
6479858
Issue Dt:
11/12/2002
Application #:
09307312
Filing Dt:
05/07/1999
Publication #:
US20020014652
Pub Dt:
02/07/2002
Title:
METHOD AND APPARATUS FOR A SEMICONDUCTOR DEVICE WITH ADJUSTABLE THRESHOLD VOLTAGE
4
Patent #:
6137333
Issue Dt:
10/24/2000
Application #:
09307588
Filing Dt:
05/07/1999
Title:
OPTIMAL DELAY CONTROLLER
5
Patent #:
6366767
Issue Dt:
04/02/2002
Application #:
09309710
Filing Dt:
05/11/1999
Title:
LOCAL OSCILLATION CIRCUIT AND A RECEIVING CIRCUIT INCLUDING THE LOCAL OSCILLATION CIRCUIT
6
Patent #:
6228782
Issue Dt:
05/08/2001
Application #:
09309994
Filing Dt:
05/11/1999
Title:
CORE FIELD ISOLATION FOR A NAND FLASH MEMORY
7
Patent #:
6114914
Issue Dt:
09/05/2000
Application #:
09314535
Filing Dt:
05/19/1999
Title:
FRACTIONAL SYNTHESIS SCHEME FOR GENERATING PERIODIC SIGNALS
8
Patent #:
6584594
Issue Dt:
06/24/2003
Application #:
09314574
Filing Dt:
05/18/1999
Title:
DATA PRE-READING AND ERROR CORRECTION CIRCUIT FOR A MEMORY DEVICE
9
Patent #:
6438726
Issue Dt:
08/20/2002
Application #:
09314575
Filing Dt:
05/18/1999
Title:
METHOD OF DUAL USE OF NON-VOLATILE MEMORY FOR ERROR CORRECTION
10
Patent #:
6381550
Issue Dt:
04/30/2002
Application #:
09322195
Filing Dt:
05/28/1999
Title:
METHOD OF UTILIZING FAST CHIP ERASE TO SCREEN ENDURANCE REJECTS
11
Patent #:
6236230
Issue Dt:
05/22/2001
Application #:
09322946
Filing Dt:
05/28/1999
Title:
METHOD, ARCHITECTURE AND CIRCUIT FOR PRODUCT TERM ALLOCATION
12
Patent #:
6214743
Issue Dt:
04/10/2001
Application #:
09326432
Filing Dt:
06/04/1999
Title:
METHOD AND STRUCTURE FOR MAKING SELF-ALIGNED CONTACTS
13
Patent #:
6496033
Issue Dt:
12/17/2002
Application #:
09326804
Filing Dt:
06/04/1999
Publication #:
US20010043081
Pub Dt:
11/22/2001
Title:
UNIVERSAL LOGIC CHIP
14
Patent #:
6160317
Issue Dt:
12/12/2000
Application #:
09336057
Filing Dt:
06/18/1999
Title:
METHOD OF SPACER FORMATION AND SOURCE PROTECTION AFTER SELF-ALIGNED SOURCE FORMED AND A DEVICE PROVIDED BY SUCH A METHOD
15
Patent #:
6181628
Issue Dt:
01/30/2001
Application #:
09339602
Filing Dt:
06/24/1999
Title:
POWER-ON-RESET CIRCUIT WITH ANALOG DELAY AND HIGH NOISE IMMUNITY
16
Patent #:
6222454
Issue Dt:
04/24/2001
Application #:
09340506
Filing Dt:
07/01/1999
Title:
NON-CONTACTING TEMPERATURE SENSING DEVICE
17
Patent #:
6147923
Issue Dt:
11/14/2000
Application #:
09343404
Filing Dt:
06/30/1999
Title:
VOLTAGE BOOSTING CIRCUIT
18
Patent #:
6101134
Issue Dt:
08/08/2000
Application #:
09344514
Filing Dt:
06/25/1999
Title:
METHOD AND CIRCUITRY FOR WRITING DATA
19
Patent #:
6890860
Issue Dt:
05/10/2005
Application #:
09345173
Filing Dt:
06/30/1999
Title:
METHOD FOR ETCHING AND/OR PATTERNING A SILICON-CONTAINING LAYER
20
Patent #:
6507932
Issue Dt:
01/14/2003
Application #:
09347074
Filing Dt:
07/02/1999
Title:
METHODS OF CONVERTING AND/OR TRANSLATING A LAYOUT OR CIRCUIT SCHEMATIC OR NETLIST THEREOF TO A SIMULATION SCHEMATIC OR NETLIST, AND/OR OF SIMULATING FUNCTION(S) AND/OR PERFORMANCE CHARACTERISTIC(S) OF A CIRCUIT
21
Patent #:
6232630
Issue Dt:
05/15/2001
Application #:
09348583
Filing Dt:
07/07/1999
Title:
LIGHT FLOATING GATE DOPING TO IMPROVE TUNNEL OXIDE RELIABILITY
22
Patent #:
6204159
Issue Dt:
03/20/2001
Application #:
09349603
Filing Dt:
07/09/1999
Title:
METHOD OF FORMING SELECT GATE TO IMPROVE RELIABILITY AND PERFORMANCE FOR NAND TYPE FLASH MEMORY DEVICES
23
Patent #:
6141237
Issue Dt:
10/31/2000
Application #:
09351563
Filing Dt:
07/12/1999
Title:
FERROELECTRIC NON-VOLATILE LATCH CIRCUITS
24
Patent #:
6235586
Issue Dt:
05/22/2001
Application #:
09352801
Filing Dt:
07/13/1999
Title:
THIN FLOATING GATE AND CONDUCTIVE SELECT GATE IN SITU DOPED AMORPHOUS SILICON MATERIAL FOR NAND TYPE FLASH MEMORY DEVICE APPLICATIONS
25
Patent #:
6240017
Issue Dt:
05/29/2001
Application #:
09353267
Filing Dt:
07/14/1999
Title:
REDUCTION OF VOLTAGE STRESS ACROSS A GATE OXIDE AND ACROSS A JUNCTION WITHIN A HIGH VOLTAGE TRANSISTOR OF AN ERASABLE MEMORY DEVICE
26
Patent #:
6433383
Issue Dt:
08/13/2002
Application #:
09357333
Filing Dt:
07/20/1999
Title:
METHODS AND ARRANGEMENTS FOR FORMING A SINGLE INTERPOLY DIELECTRIC LAYER IN A SEMICONDUCTOR DEVICE
27
Patent #:
6696855
Issue Dt:
02/24/2004
Application #:
09357716
Filing Dt:
07/20/1999
Title:
SYMMETRIC LOGIC BLOCK INPUT/OUTPUT SCHEME
28
Patent #:
6708244
Issue Dt:
03/16/2004
Application #:
09359465
Filing Dt:
07/22/1999
Publication #:
US20030046475
Pub Dt:
03/06/2003
Title:
OPTIMIZED I2O MESSAGING UNIT
29
Patent #:
6268624
Issue Dt:
07/31/2001
Application #:
09364982
Filing Dt:
07/31/1999
Title:
METHOD FOR INHIBITING TUNNEL OXIDE GROWTH AT THE EDGES OF A FLOATING GATE DURING SEMICONDUCOR DEVICE PROCESSING
30
Patent #:
6530068
Issue Dt:
03/04/2003
Application #:
09366369
Filing Dt:
08/03/1999
Title:
DEVICE MODELING AND CHARACTERIZATION STRUCTURE WITH MULTIPLEXED PADS
31
Patent #:
6300658
Issue Dt:
10/09/2001
Application #:
09368073
Filing Dt:
08/03/1999
Title:
METHOD FOR REDUCED GATE ASPECT RATIO TO IMPROVE GAP-FILL AFTER SPACER ETCH
32
Patent #:
6323047
Issue Dt:
11/27/2001
Application #:
09368247
Filing Dt:
08/03/1999
Title:
METHOD FOR MONITORING SECOND GATE OVER-ETCH IN A SEMICONDUCTOR DEVICE
33
Patent #:
6188606
Issue Dt:
02/13/2001
Application #:
09369600
Filing Dt:
08/06/1999
Title:
MULTI STATE SENSING OF NAND MEMORY CELLS BY VARYING SOURCE BIAS
34
Patent #:
6218689
Issue Dt:
04/17/2001
Application #:
09369638
Filing Dt:
08/06/1999
Title:
METHOD FOR PROVIDING A DOPANT LEVEL FOR POLYSILICON FOR FLASH MEMORY DEVICES
35
Patent #:
6166951
Issue Dt:
12/26/2000
Application #:
09370010
Filing Dt:
08/06/1999
Title:
MULTI STATE SENSING OF NAND MEMORY CELLS BY APPLYING REVERSE-BIAS VOLTAGE
36
Patent #:
6172909
Issue Dt:
01/09/2001
Application #:
09370380
Filing Dt:
08/09/1999
Title:
RAMPED GATE TECHNIQUE FOR SOFT PROGRAMMING TO TIGHTEN THE VT DISTRIBUTION
37
Patent #:
6161507
Issue Dt:
12/19/2000
Application #:
09370411
Filing Dt:
08/09/1999
Title:
TUBE PROTECTION DEVICES AND METHODS
38
Patent #:
6204685
Issue Dt:
03/20/2001
Application #:
09370669
Filing Dt:
08/09/1999
Title:
DUAL-FUNCTION METHOD AND CIRCUIT FOR PROGRAMMABLE DEVICE
39
Patent #:
6442657
Issue Dt:
08/27/2002
Application #:
09371237
Filing Dt:
08/10/1999
Title:
FLAG GENERATION SCHEME FOR FIFOS
40
Patent #:
6218969
Issue Dt:
04/17/2001
Application #:
09372344
Filing Dt:
08/11/1999
Title:
UNIVERSAL SERIAL BUS TO PARALLEL BUS SIGNAL CONVERTER AND METHOD OF CONVERSION
41
Patent #:
6580639
Issue Dt:
06/17/2003
Application #:
09372406
Filing Dt:
08/10/1999
Title:
METHOD OF REDUCING PROGRAM DISTURBS IN NAND TYPE FLASH MEMORY DEVICES
42
Patent #:
6388469
Issue Dt:
05/14/2002
Application #:
09373870
Filing Dt:
08/13/1999
Title:
MULTIPLE POWER SUPPLY OUTPUT DRIVER
43
Patent #:
6383939
Issue Dt:
05/07/2002
Application #:
09375504
Filing Dt:
08/17/1999
Title:
METHOD FOR ETCHING MEMORY GATE STACK USING THIN RESIST LAYER
44
Patent #:
6808996
Issue Dt:
10/26/2004
Application #:
09376659
Filing Dt:
08/18/1999
Title:
METHOD FOR PROTECTING GATE EDGES FROM CHARGE GAIN/LOSS IN SEMICONDUCTOR DEVICE
45
Patent #:
6252276
Issue Dt:
06/26/2001
Application #:
09377183
Filing Dt:
08/19/1999
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING ASSYMETRICALLY NITROGEN DOPED GATE OXIDE
46
Patent #:
6088287
Issue Dt:
07/11/2000
Application #:
09379479
Filing Dt:
08/23/1999
Title:
FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT FOR WORD LINE DECODING
47
Patent #:
6323683
Issue Dt:
11/27/2001
Application #:
09384510
Filing Dt:
08/27/1999
Title:
LOW DISTORTION LOGIC LEVEL TRANSLATOR
48
Patent #:
6242790
Issue Dt:
06/05/2001
Application #:
09385550
Filing Dt:
08/30/1999
Title:
USING POLYSILICON FUSE FOR IC PROGRAMMING
49
Patent #:
6411069
Issue Dt:
06/25/2002
Application #:
09387018
Filing Dt:
08/31/1999
Title:
CONTINOUS CAPACITOR DIVIDER SAMPLED REGULATION SCHEME
50
Patent #:
6418054
Issue Dt:
07/09/2002
Application #:
09387421
Filing Dt:
08/31/1999
Title:
EMBEDDED METHODOLOGY TO PROGRAM/ERASE REFERENCE CELLS USED IN SENSING FLASH CELLS
51
Patent #:
6576949
Issue Dt:
06/10/2003
Application #:
09387710
Filing Dt:
08/30/1999
Title:
INTEGRATED CIRCUIT HAVING OPTIMIZED GATE COUPLING CAPACITANCE
52
Patent #:
6141244
Issue Dt:
10/31/2000
Application #:
09388696
Filing Dt:
09/02/1999
Title:
MULTI LEVEL SENSING OF NAND MEMORY CELLS BY EXTERNAL BIAS CURRENT
53
Patent #:
6141255
Issue Dt:
10/31/2000
Application #:
09389161
Filing Dt:
09/02/1999
Title:
1 TRANSISTOR CELL FOR EEPROM APPLICATION
54
Patent #:
6323516
Issue Dt:
11/27/2001
Application #:
09390052
Filing Dt:
09/03/1999
Title:
FLASH MEMORY DEVICE AND FABRICATION METHOD HAVING A HIGH COUPLING RATIO
55
Patent #:
6194965
Issue Dt:
02/27/2001
Application #:
09390591
Filing Dt:
09/03/1999
Title:
DIFFERENTIAL SIGNAL DETECTION CIRCUIT
56
Patent #:
6287917
Issue Dt:
09/11/2001
Application #:
09392675
Filing Dt:
09/08/1999
Title:
PROCESS FOR FABRICATING AN MNOS FLASH MEMORY DEVICE
57
Patent #:
6302766
Issue Dt:
10/16/2001
Application #:
09394819
Filing Dt:
09/13/1999
Title:
SYSTEM FOR CLEANING A SURFACE OF A DIELECTRIC MATERIAL
58
Patent #:
6327175
Issue Dt:
12/04/2001
Application #:
09395057
Filing Dt:
09/13/1999
Title:
METHOD AND APPARATUS FOR CONTROLLING A MEMORY ARRAY WITH A PROGRAMMABLE REGISTER
59
Patent #:
6292013
Issue Dt:
09/18/2001
Application #:
09396024
Filing Dt:
09/15/1999
Title:
COLUMN REDUNDANCY SCHEME FOR BUS-MATCHING FIFOS
60
Patent #:
6229345
Issue Dt:
05/08/2001
Application #:
09396344
Filing Dt:
09/15/1999
Title:
HIGH SPEED CHARGE-PUMP
61
Patent #:
6526470
Issue Dt:
02/25/2003
Application #:
09398736
Filing Dt:
09/17/1999
Title:
FIFO BUS-SIZING, BUS-MATCHING DATAPATH ARCHITECTURE
62
Patent #:
6239632
Issue Dt:
05/29/2001
Application #:
09398936
Filing Dt:
09/17/1999
Title:
METHOD, ARCHITECTURE AND/OR CIRCUITRY FOR CONTROLLING THE PULSE WIDTH IN A PHASE AND/OR FREQUENCY DETECTOR
63
Patent #:
6704381
Issue Dt:
03/09/2004
Application #:
09398956
Filing Dt:
09/17/1999
Title:
FREQUENCY ACQUISITION RATE CONTROL IN PHASE LOCK LOOP CIRCUITS
64
Patent #:
6380033
Issue Dt:
04/30/2002
Application #:
09399414
Filing Dt:
09/20/1999
Title:
PROCESS TO IMPROVE READ DISTURB FOR NAND FLASH MEMORY DEVICES
65
Patent #:
6284602
Issue Dt:
09/04/2001
Application #:
09399526
Filing Dt:
09/20/1999
Title:
PROCESS TO REDUCE POST CYCLING PROGRAM VT DISPERSION FOR NAND FLASH MEMORY DEVICES
66
Patent #:
6191636
Issue Dt:
02/20/2001
Application #:
09400685
Filing Dt:
09/22/1999
Title:
INPUT BUFFER/LEVEL SHIFTER
67
Patent #:
6530040
Issue Dt:
03/04/2003
Application #:
09401614
Filing Dt:
09/22/1999
Title:
PARALLEL TEST IN ASYNCHRONOUS MEMORY WITH SINGLE-ENDED OUTPUT PATH
68
Patent #:
6172914
Issue Dt:
01/09/2001
Application #:
09404078
Filing Dt:
09/23/1999
Title:
CONCURRENT ERASE VERIFY SCHEME FOR FLASH MEMORY APPLICATIONS
69
Patent #:
6049479
Issue Dt:
04/11/2000
Application #:
09404080
Filing Dt:
09/23/1999
Title:
OPERATIONAL APPROACH FOR THE SUPPRESSION OF BI-DIRECTIONAL TUNNEL OXIDE STRESS OF A FLASH CELL
70
Patent #:
6369416
Issue Dt:
04/09/2002
Application #:
09404394
Filing Dt:
09/23/1999
Title:
SEMICONDUCTOR DEVICE WITH CONTACTS HAVING A SLOPED PROFILE
71
Patent #:
6342415
Issue Dt:
01/29/2002
Application #:
09404395
Filing Dt:
09/23/1999
Publication #:
US20020025618
Pub Dt:
02/28/2002
Title:
METHOD AND SYSTEM FOR PROVIDING REDUCED-SIZED CONTACTS IN A SEMICONDUCTOR DEVICE
72
Patent #:
6734108
Issue Dt:
05/11/2004
Application #:
09405945
Filing Dt:
09/27/1999
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING CONTACTS IN A SEMICONDUCTOR STRUCTURE
73
Patent #:
6088289
Issue Dt:
07/11/2000
Application #:
09405950
Filing Dt:
09/27/1999
Title:
CIRCUIT AND METHOD FOR CONTROLLING A WORDLINE AND/OR STABILIZING A MEMORY CELL
74
Patent #:
7062425
Issue Dt:
06/13/2006
Application #:
09410160
Filing Dt:
09/30/1999
Title:
METHOD AND APPARATUS FOR AUTOMATED ENUMERATION, SIMULATION, IDENTIFICATION AND/OR IRRADIATION OF DEVICE ATTRIBUTES
75
Patent #:
6452441
Issue Dt:
09/17/2002
Application #:
09411169
Filing Dt:
10/01/1999
Title:
LOW THRESHOLD VOLTAGE DEVICE WITH CHARGE PUMP FOR REDUCING STANDBY CURRENT IN AN INTEGRATED CIRCUIT HAVING REDUCED SUPPLY VOLTAGE
76
Patent #:
6177316
Issue Dt:
01/23/2001
Application #:
09412278
Filing Dt:
10/05/1999
Title:
POST BARRIER METAL CONTACT IMPLANTATION TO MINIMIZE OUT DIFFUSION FOR NAND DEVICE
77
Patent #:
6235584
Issue Dt:
05/22/2001
Application #:
09412544
Filing Dt:
10/05/1999
Title:
METHOD AND SYSTEM FOR REDUCING SHORT CHANNEL EFFECTS IN A MEMORY DEVICE
78
Patent #:
6122198
Issue Dt:
09/19/2000
Application #:
09413182
Filing Dt:
10/05/1999
Title:
BIT BY BIT APDE VERIFY FOR FLASH MEMORY APPLICATIONS
79
Patent #:
6506683
Issue Dt:
01/14/2003
Application #:
09413621
Filing Dt:
10/06/1999
Title:
IN-SITU PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE WITH INTEGRAL REMOVAL OF ANTIREFLECTION AND ETCH STOP LAYERS
80
Patent #:
6291296
Issue Dt:
09/18/2001
Application #:
09416382
Filing Dt:
10/12/1999
Title:
METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS BEFORE CONTACT CMP
81
Patent #:
6136649
Issue Dt:
10/24/2000
Application #:
09416389
Filing Dt:
10/12/1999
Title:
METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS AFTER CONTACT CMP
82
Patent #:
6275415
Issue Dt:
08/14/2001
Application #:
09416563
Filing Dt:
10/12/1999
Title:
MULTIPLE BYTE CHANNEL HOT ELECTRON PROGRAMMING USING RAMPED GATE AND SOURCE BIAS VOLTAGE
83
Patent #:
6197635
Issue Dt:
03/06/2001
Application #:
09417130
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED MASKING AND WITHOUT ARC LOSS IN PERIPHERAL CIRCUITRY REGION
84
Patent #:
6235587
Issue Dt:
05/22/2001
Application #:
09417131
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH REDUCED ARC LOSS IN PERIPHERAL CIRCUITRY REGION
85
Patent #:
6200857
Issue Dt:
03/13/2001
Application #:
09417132
Filing Dt:
10/13/1999
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITHOUT ARC LOSS IN PERIPHERAL CIRCUIT REGION
86
Patent #:
6118694
Issue Dt:
09/12/2000
Application #:
09417731
Filing Dt:
10/14/1999
Title:
DISTRIBUTING CFI DEVICES IN EXISTING DECODERS
87
Patent #:
6144606
Issue Dt:
11/07/2000
Application #:
09417732
Filing Dt:
10/14/1999
Title:
METHOD AND SYSTEM FOR BI-DIRECTIONAL VOLTAGE REGULATION DETECTION
88
Patent #:
6147906
Issue Dt:
11/14/2000
Application #:
09419695
Filing Dt:
10/14/1999
Title:
METHOD AND SYSTEM FOR SAVING OVERHEAD PROGRAM TIME IN A MEMORY DEVICE
89
Patent #:
6185130
Issue Dt:
02/06/2001
Application #:
09420209
Filing Dt:
10/18/1999
Title:
PROGRAMMABLE CURRENT SOURCE
90
Patent #:
6255165
Issue Dt:
07/03/2001
Application #:
09420220
Filing Dt:
10/18/1999
Title:
NITRIDE PLUG TO REDUCE GATE EDGE LIFTING
91
Patent #:
6201753
Issue Dt:
03/13/2001
Application #:
09421142
Filing Dt:
10/19/1999
Title:
LATCHING CAM DATA IN A FLASH MEMORY DEVICE
92
Patent #:
6344281
Issue Dt:
02/05/2002
Application #:
09421333
Filing Dt:
10/18/1999
Title:
ALUMINUM METALLIZATION METHOD AND PRODUCT
93
Patent #:
6285585
Issue Dt:
09/04/2001
Application #:
09421471
Filing Dt:
10/19/1999
Title:
OUTPUT SWITCHING IMPLEMENTATION FOR A FLASH MEMORY DEVICE
94
Patent #:
6331950
Issue Dt:
12/18/2001
Application #:
09421757
Filing Dt:
10/19/1999
Title:
WRITE PROTECT INPUT IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
95
Patent #:
6163478
Issue Dt:
12/19/2000
Application #:
09421774
Filing Dt:
10/19/1999
Title:
COMMON FLASH INTERFACE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
96
Patent #:
6327181
Issue Dt:
12/04/2001
Application #:
09421775
Filing Dt:
10/19/1999
Title:
REFERENCE CELL BITLINE PATH ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
97
Patent #:
6111787
Issue Dt:
08/29/2000
Application #:
09421776
Filing Dt:
10/19/1999
Title:
ADDRESS TRANSISTION DETECT TIMING ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
98
Patent #:
6185128
Issue Dt:
02/06/2001
Application #:
09421984
Filing Dt:
10/19/1999
Title:
REFERENCE CELL FOUR-WAY SWITCH FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
99
Patent #:
6359808
Issue Dt:
03/19/2002
Application #:
09421985
Filing Dt:
10/19/1999
Title:
LOW VOLTAGE READ CASCODE FOR 2V/3V AND DIFFERENT BANK COMBINATIONS WITHOUT METAL OPTIONS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
100
Patent #:
6259633
Issue Dt:
07/10/2001
Application #:
09422198
Filing Dt:
10/19/1999
Title:
SENSE AMPLIFIER ARCHITECTURE FOR SLIDING BANKS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
Assignor
1
CYPRESS SEMICONDUCTOR CORPORATION
Exec Dt:
08/11/2016
Assignee
1
MONTEREY RESEARCH, LLC
3945 FREEDOM CIRCLE
SUITE 900
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
LONGITUDE LICENSING LTD
1ST FLOOR, EUROPA HOUSE
HARCOURT CENTRE, HARCOURT STREET
DUBLIN 2, D02 WR20 IRELAND

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