|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09422199
|
Filing Dt:
|
10/19/1999
|
|
Title:
|
OUTPUT MULTIPLEXING IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09426100
|
Filing Dt:
|
10/22/1999
|
|
Title:
|
SILICON-OXIDE-NITRIDE-OXIDE-SEMICONDUCTOR (SONOS) TYPE MEMORY CELL AND METHOD FOR RETAINING DATA IN THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09426205
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
PROCESS FOR FABRICATING A BIT-LINE IN A MONOS DEVICE USING A DUAL LAYER HARD MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09426239
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
METHOD TO GENERATE A MONOS TYPE FLASH CELL USING POLYCRYSTALLINE SILICON AS AN ONO TOP LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09426255
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
METHOD OF USING SOURCE/DRAIN NITRIDE FOR PERIPHERY FIELD OXIDE AND BIT-LINE OXIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09426427
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
METHOD OF FABRICATING A MONOS FLASH CELL USING SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09426430
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
METHOD OF FABRICATING AN ONO DIELECTRIC BY NITRIDATION FOR MNOS MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09426672
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
HIGH TEMPERATURE OXIDE DEPOSITION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO BIT EEPROM DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2001
|
Application #:
|
09426743
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
PROCESS FOR FORMING A BIT-LINE IN A MONOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09426757
|
Filing Dt:
|
10/26/1999
|
|
Title:
|
MICROPROCESSOR FOR CONTROLLING BUSSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09427402
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
INTEGRATED METHOD BY USING HIGH TEMPERATURE OXIDE FOR TOP OXIDE AND PERIPHERY GATE OXIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09427404
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
PROCESS FOR FABRICATING A BIT-LINE USING BURIED DIFFUSION ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2001
|
Application #:
|
09427644
|
Filing Dt:
|
10/27/1999
|
|
Title:
|
MULTI-LAYER APPROACH FOR OPTIMIZING FERROELECTRIC FILM PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09428624
|
Filing Dt:
|
10/27/1999
|
|
Title:
|
CIRCUIT AND METHOD FOR PREVENTING RUNAWAY IN A PHASE LOCK LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09429722
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A METALLIC HARD MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09430336
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
BIASING SCHEME TO REDUCE STRESS ON NON-SELECTED CELLS DURING READ
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
09430366
|
Filing Dt:
|
10/28/1999
|
|
Title:
|
METHOD OF MAKING A MEMORY CELL WITH POLISHED INSULATOR LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
09430410
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
SOLID-SOURCE DOPING FOR SOURCE/DRAIN TO ELIMINATE IMPLANT DAMAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09430493
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS USING A POLYSILICON HARD MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09430765
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
METHOD FOR FORMING FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09430848
|
Filing Dt:
|
11/01/1999
|
|
Title:
|
SPACER NARROWED, DUAL WIDTH CONTACT FOR CHARGE GAIN REDUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09433037
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
NITRIDATION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO-BIT EEPROM DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
09433041
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
PROCESS FOR FABRICATING AN ONO STRUCTURE HAVING A SILICON-RICH SILICON NITRIDE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09433186
|
Filing Dt:
|
10/25/1999
|
|
Title:
|
PROCESS FOR FABRICATING AN ONO STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09433822
|
Filing Dt:
|
11/03/1999
|
|
Title:
|
CIRCUIT, ARCHITECTURE AND METHOD FOR REDUCING POWER CONSUMPTION IN A SYNCHRONOUS INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
09434908
|
Filing Dt:
|
11/05/1999
|
|
Title:
|
APPARATUS AND METHOD FOR CONTROLLING AN ELECTRONIC PRESENTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09436155
|
Filing Dt:
|
11/09/1999
|
|
Title:
|
CIRCUIT AND METHOD FOR LINEAR CONTROL OF A SPREAD SPECTRUM TRANSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09436503
|
Filing Dt:
|
11/09/1999
|
|
Title:
|
DOUBLE DENSITY NON-VOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09440934
|
Filing Dt:
|
11/16/1999
|
|
Title:
|
SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2003
|
Application #:
|
09441134
|
Filing Dt:
|
11/17/1999
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
SELECTOR AND MULTILAYER INTERCONNECTION WITH REDUCED OCCUPIED AREA ON SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2002
|
Application #:
|
09441649
|
Filing Dt:
|
11/17/1999
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2002
| | | | |
|
Title:
|
CIRCUITS, ARCHITECTURES, AND METHODS FOR GENERATING A PERIODIC SIGNAL IN A MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09442851
|
Filing Dt:
|
11/18/1999
|
|
Title:
|
ARCHITECTURE, CIRCUITRY AND METHOD FOR CONFIGURING VOLATILE AND/OR NON-VOLATILE MEMORY FOR PROGRAMMABLE LOGIC APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09451958
|
Filing Dt:
|
11/30/1999
|
|
Title:
|
MOS OUTPUT DRIVER, AND CIRCUIT AND METHOD OF CONTROLLING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09451959
|
Filing Dt:
|
11/30/1999
|
|
Title:
|
METHOD AND APPARATUS FOR THE AUTOMATED GENERATION OF SINGLE AND MULTISTAGE PROGRAMMABLE INTERCONNECT MATRICES WITH AUTOMATIC ROUTING TOOLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09456801
|
Filing Dt:
|
12/08/1999
|
|
Title:
|
NON-VOLATILE INVERTER LATCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
09458552
|
Filing Dt:
|
12/09/1999
|
|
Title:
|
Tristate output buffer with matched signals to pmos and nmos output transistors
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09461376
|
Filing Dt:
|
12/15/1999
|
|
Title:
|
BIASING METHOD AND STRUCTURE FOR REDUCING BAND-TO-BAND AND/OR AVALANCHE CURRENTS DURING THE ERASE OF FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09461632
|
Filing Dt:
|
12/15/1999
|
|
Title:
|
BLOCK REDUNDANCY IN ULTRA LOW POWER MEMORY CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2003
|
Application #:
|
09465067
|
Filing Dt:
|
12/16/1999
|
|
Title:
|
METHOD AND ARCHITECTURE FOR RE-PROGRAMMING CONVENTIONALLY NON-REPROGRAMMABLE TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2002
|
Application #:
|
09467098
|
Filing Dt:
|
12/10/1999
|
|
Title:
|
DUAL THRESHOLD DELAY MEASUREMENT/SCALING SCHEME TO AVOID NEGATIVE AND NON-MONOTONIC DELAY PARAMETERS IN TIMING ANALYSIS/CHARACTERIZATION OF CIRCUIT BLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09468938
|
Filing Dt:
|
12/22/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING CURRENT AUXILIARY CIRCUIT FOR OUTPUT CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09470568
|
Filing Dt:
|
12/22/1999
|
|
Title:
|
FULLY RECESSED SEMICONDUCTOR METHOD FOR LOW POWER APPLICATIONS WITH SINGLE WRAP AROUND BURIED DRAIN REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09475808
|
Filing Dt:
|
12/30/1999
|
|
Title:
|
CONFIGURABLE MEMORY FOR PROGRAMMABLE LOGIC CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09476121
|
Filing Dt:
|
01/03/2000
|
|
Title:
|
METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09476584
|
Filing Dt:
|
01/03/2000
|
|
Title:
|
USE OF ETCH TO BLUNT GATE CORNERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
09476669
|
Filing Dt:
|
12/30/1999
|
|
Title:
|
METHOD FOR FORMING A METALLIZATION STRUCTURE IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09476923
|
Filing Dt:
|
01/04/2000
|
|
Title:
|
1376123452182SYSTEM FOR RECONFIGURING A PERIPHERAL DEVICE BY DOWNLOADING INFORMATION FROM A HOST AND ELECTRONICALLY SIMULATE A PHYSICAL DISCONNECTION AND RECONNECTION TO RECONFIGURE THE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09478864
|
Filing Dt:
|
01/07/2000
|
|
Title:
|
METHOD AND SYSTEM FOR USING A SPACER TO OFFSET IMPLANT DAMAGE AND REDUCE LATERAL DIFFUSION IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09483557
|
Filing Dt:
|
01/14/2000
|
|
Title:
|
Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2002
|
Application #:
|
09484975
|
Filing Dt:
|
01/18/2000
|
|
Title:
|
METHOD, ARCHITECTURE AND CIRCUITRY FOR INDEPENDENTLY CONFIGURING A MULTIPLE ARRAY MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09487073
|
Filing Dt:
|
01/19/2000
|
|
Title:
|
Process for fabricating an eeprom device having a pocket substrate region
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09487922
|
Filing Dt:
|
01/19/2000
|
|
Title:
|
Process for fabricating a semiconductor device having a graded junction
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09489256
|
Filing Dt:
|
01/21/2000
|
|
Title:
|
Apparatus for transferring a plurlity of integrated circuit devices into and/or out of a plurality of sockets
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09490352
|
Filing Dt:
|
01/24/2000
|
|
Title:
|
Background correction for charge gain and loss
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09490353
|
Filing Dt:
|
01/24/2000
|
|
Title:
|
Reduction of oxide stress through the use of forward biased body voltage
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
09491044
|
Filing Dt:
|
01/25/2000
|
|
Title:
|
CONTACT STRUCTURE AND METHOD OF FORMING A CONTACT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
09492243
|
Filing Dt:
|
01/27/2000
|
|
Title:
|
METHOD AND APPARATUS FOR IMPROVED PERFORMANCE OF FLASH MEMORY CELL DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
09492353
|
Filing Dt:
|
01/27/2000
|
|
Title:
|
Two bit flash cell with two floating gate regions
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2002
|
Application #:
|
09493436
|
Filing Dt:
|
01/29/2000
|
|
Title:
|
METHOD FOR FORMING SELF-ALIGNED CONTACTS AND INTERCONNECTION LINES USING DUAL DAMASCENE TECHNIQUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2001
|
Application #:
|
09495213
|
Filing Dt:
|
01/31/2000
|
|
Title:
|
Nitridization of the pre-ddi screen oxide
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09498205
|
Filing Dt:
|
02/04/2000
|
|
Title:
|
Noise reduction during simultaneous operation of a flash memory device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09499816
|
Filing Dt:
|
02/08/2000
|
|
Title:
|
High performance product term based carry chain scheme
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09501159
|
Filing Dt:
|
02/09/2000
|
|
Title:
|
Voltage boost reset circuit for a flash memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09501246
|
Filing Dt:
|
02/10/2000
|
|
Title:
|
STATIC TIMING ANALYSIS WITH SIMULATIONS ON CRITICAL PATH NETLISTS GENERATED BY STATIS TIMING ANALYSIS TOOLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2003
|
Application #:
|
09504344
|
Filing Dt:
|
02/14/2000
|
|
Title:
|
MEMORY DEVICE WITH FIXED LENGTH NON-INTERRUPTIBLE BURST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09504696
|
Filing Dt:
|
02/16/2000
|
|
Title:
|
Method of maintaining constant erasing speeds for non-volatile memory cells
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09505106
|
Filing Dt:
|
02/15/2000
|
|
Title:
|
METHOD OF FABRICATING PARTIALLY OR COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09505259
|
Filing Dt:
|
02/16/2000
|
|
Title:
|
Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09506298
|
Filing Dt:
|
02/17/2000
|
|
Title:
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ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
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Patent #:
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Issue Dt:
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06/25/2002
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Application #:
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09507810
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Filing Dt:
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02/22/2000
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Title:
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METHOD FOR REMOVING SEMICONDUCTOR ARC USING ARC CMP BUFFING
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09511019
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Filing Dt:
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02/23/2000
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Title:
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AUTO-LOCKING OSCILLATOR FOR DATA COMMUNICATIONS
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09511020
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Filing Dt:
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02/23/2000
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Title:
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Circuit for locking an oscillator to a data stream
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Patent #:
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Issue Dt:
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05/01/2001
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Application #:
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09512617
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Filing Dt:
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02/25/2000
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Title:
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High speed, high precision, power supply and process independent boost level clamping technique
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09512854
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Filing Dt:
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02/25/2000
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Title:
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Dynamic memory cell programming voltage
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09513260
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Filing Dt:
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02/24/2000
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Title:
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DOUBLE SELF-ALIGNING SHALLOW TRENCH ISOLATION SEMICONDUCTOR AND MANUFACTURING METHOD THEREFOR
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09513261
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Filing Dt:
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02/24/2000
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Title:
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SEMICONDUCTOR WITH INCREASED GATE COUPLING COEFFICIENT
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09513402
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Filing Dt:
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02/25/2000
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Title:
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MODE INDICATOR FOR MULTI-LEVEL MEMORY
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09515549
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Filing Dt:
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02/29/2000
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Title:
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Trans-Impedance amplifier
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09516472
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Filing Dt:
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03/01/2000
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Title:
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FLASH MEMORY CELLS HAVING A MODULATION DOPED HETEROJUNCTION STRUCTURE
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09521190
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Filing Dt:
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03/07/2000
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Title:
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Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09522247
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Filing Dt:
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03/09/2000
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Title:
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NAND FLASH MEMORY WITH SPECIFIED GATE OXIDE THICKNESS
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09523816
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Filing Dt:
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03/13/2000
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Title:
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Wordline voltage protection
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09525078
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Filing Dt:
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03/14/2000
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Title:
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CHAINED ARRAY OF SEQUENTIAL ACCESS MEMORIES ENABLING CONTINUOUS READ
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09525955
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Filing Dt:
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03/15/2000
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Title:
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Heterogeneous CPLD logic blocks
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09526239
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Filing Dt:
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03/15/2000
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Title:
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Multiple bank simultaneous operation for a flash memory
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09527715
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Filing Dt:
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03/17/2000
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Title:
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REAL TIME PROGRAMMABLE FEATURE CONTROL FOR PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09531241
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Filing Dt:
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03/21/2000
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Title:
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ENDIAN-CONTROLLED COUNTER FOR SYNCHRONOUS PORTS WITH BUS MATCHING
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09531365
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Filing Dt:
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03/21/2000
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Title:
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CIRCUIT, ARCHITECTURE AND METHOD FOR READING AN ADDRESS COUNTER AND/OR MATCHING A BUS WIDTH THROUGH ONE OR MORE SYNCHRONOUS PORTS
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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09531677
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Filing Dt:
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03/20/2000
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Title:
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PHASE COMPARATOR AND METHOD OF CONTROLLING POWER SAVING OPERATION OF THE SAME, AND SEMICONDUCTOR INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/13/2001
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Application #:
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09531749
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Filing Dt:
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03/20/2000
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Title:
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A METHOD OF FORMING A NAND -TYPE FLASH MEMORY DEVICE H AVING A NON-STACKED SELECT GATE TRANSISTOR STRUCTURE
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09532293
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Filing Dt:
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03/23/2000
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Title:
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FLASH MEMORY WITH LESS SUSCEPTIBILITY TO CHARGE GAIN AND CHARGE LOSS
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09532545
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Filing Dt:
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03/22/2000
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Title:
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MULTIPORT FIFO WITH PROGRAMMABLE WIDTH AND DEPTH
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09532582
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Filing Dt:
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03/22/2000
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Title:
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Oscillator based power-on-reset circuit
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09533617
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Filing Dt:
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03/22/2000
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Title:
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METHOD AND SYSTEM FOR REDUCING CHARGE GAIN AND CHARGE LOSS IN INTERLAYER DIELECTRIC FORMATION
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09533631
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Filing Dt:
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03/22/2000
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Title:
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ON-CHIP CIRCUIT TO COMPENSATE OUTPUT DRIVE STRENGTH ACROSS PROCESS CORNERS
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09533740
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Filing Dt:
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03/23/2000
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Title:
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Phase alignment system
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09534671
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Filing Dt:
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03/24/2000
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Title:
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Memory architecture
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09534760
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Filing Dt:
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03/24/2000
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Title:
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Memory architecture
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09537376
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Filing Dt:
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03/29/2000
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Title:
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METHOD AND APPARATUS FOR USING A PHASE LOCK LOOP TO GENERATE OUTPUT STATUS AND CLOCKING SIGNALS IN RESPONSE TO INPUT CLOCKING, CONFIGURATION, AND FEEDBACK SIGNALS
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09538201
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Filing Dt:
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03/30/2000
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Title:
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METHOD FOR USING A RECOVERED DATA-ENCODED CLOCK TO CONVERT HIGH-FREQUENCY SERIAL DATA TO LOWER FREQUENCY PARALLEL DATA
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