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Patent #:
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Issue Dt:
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10/15/2002
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09788838
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02/20/2001
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Title:
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MULTIPLEXERS FOR EFFICIENT PLD LOGIC BLOCKS
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Patent #:
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Issue Dt:
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08/27/2002
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09789052
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02/20/2001
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Title:
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MULTIPLEXERS FOR EFFICIENT PLD LOGIC BLOCKS
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Patent #:
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Issue Dt:
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11/02/2004
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09791355
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02/23/2001
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Title:
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EMC ENHANCEMENT FOR DIFFERENTIAL DEVICES
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Issue Dt:
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11/11/2003
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09791874
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02/26/2001
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Publication #:
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Pub Dt:
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02/28/2002
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Title:
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PROCESSOR CAPABLE OF ENABLING/DISABLING MEMORY ACCESS
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Patent #:
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04/04/2006
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09793359
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02/26/2001
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Title:
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HIGH VOLTAGE SWITCH WITH NO LATCH-UP HAZARDS
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Patent #:
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Issue Dt:
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09/02/2003
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09794480
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02/26/2001
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Title:
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ASCENDING STAIRCASE READ TECHNIQUE FOR A MULTILEVEL CELL NAND FLASH MEMORY DEVICE
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Issue Dt:
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03/25/2003
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09794482
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Filing Dt:
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02/26/2001
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Title:
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STAIRCASE PROGRAM VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Patent #:
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Issue Dt:
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11/12/2002
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09796549
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03/02/2001
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Pub Dt:
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03/14/2002
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Title:
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ACTIVE LOAD CIRCUIT, AND OPERATIONAL AMPLIFIER AND COMPARATOR HAVING THE SAME
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03/18/2003
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09803400
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03/12/2001
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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HIGH VOLTAGE OXIDATION METHOD FOR HIGHLY RELIABLE FLASH MEMORY DEVICES
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01/18/2005
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09804523
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03/12/2001
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Title:
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CONFIGURABLE DEDICATED LOGIC IN PLDS
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04/01/2003
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09808488
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03/13/2001
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Title:
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OUTPUT BUFFER METHOD AND APPARATUS WITH ON RESISTANCE AND SKEW CONTROL
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Patent #:
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02/04/2003
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09809208
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03/16/2001
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Pub Dt:
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12/20/2001
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Title:
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FRACTIONAL-N-PILL FREQUENCY SYNTHESIZER AND PHASE ERROR CANCELING METHOD THEREFOR
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Patent #:
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Issue Dt:
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02/11/2003
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09809221
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03/16/2001
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Pub Dt:
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01/24/2002
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Title:
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PLL FREQUENCY SYNTHESIZER CIRCUIT
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Issue Dt:
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01/14/2003
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09809242
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03/15/2001
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Title:
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PARALLEL CONFIGURATION METHOD AND/OR ARCHITECTURE FOR PLDS OR FPGAS
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Patent #:
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04/23/2002
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09811288
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03/16/2001
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Pub Dt:
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08/23/2001
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Title:
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Method for reduced gate aspect ratio to improve gap-fill after spacer etch
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Patent #:
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Issue Dt:
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07/06/2004
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09812109
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03/19/2001
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Pub Dt:
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09/19/2002
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Title:
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CONFIGURABLE AND MEMORY ARCHITECTURE INDEPENDENT MEMORY BUILT-IN SELF TEST
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Patent #:
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Issue Dt:
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01/07/2003
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09812475
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03/19/2001
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Publication #:
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Pub Dt:
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08/09/2001
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Title:
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UNIVERSAL SERIAL BUS PERIPHERAL BRIDGE WITH SEQUENCER
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09816749
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03/26/2001
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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TRIMMING CIRCUIT OF SEMICONDUCTOR APPARATUS
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09817628
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Filing Dt:
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03/26/2001
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Title:
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FORMATION OF NON-VOLATILE MEMORY DEVICE COMPRISED OF AN ARRAY OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURES
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Patent #:
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Issue Dt:
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11/29/2005
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09819592
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03/27/2001
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Title:
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METHOD OF EMAIL ATTACHMENT CONFIRMATION
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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09821006
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Filing Dt:
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03/29/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A UNIVERSAL SERIAL BUS DEVICE
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09821680
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Filing Dt:
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03/29/2001
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Title:
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METHOD AND APPARATUS FOR ACCURATELY READING A POTENTIOMETER
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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09823414
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Filing Dt:
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03/31/2001
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Title:
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INTELLIGENT, EXTENSIBLE SIE PERIPHERAL DEVICE
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09823530
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Filing Dt:
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03/30/2001
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Title:
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METHOD FOR POLISHING A SEMICONDUCTOR TOPOGRAPHY
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09824841
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Filing Dt:
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04/02/2001
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Title:
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Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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09825027
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Filing Dt:
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04/02/2001
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Title:
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CLOCKED BASED METHOD AND DEVICES FOR MEASURING VOLTAGE-VARIABLE CAPACITANCES AND OTHER ON-CHIP PARAMETERS
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09825899
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Filing Dt:
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04/03/2001
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Title:
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CASCADABLE BUS BASED CROSSBAR SWITCH IN A PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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09826998
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Filing Dt:
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04/03/2001
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Title:
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EXECUTABLE CODE DERIVED FROM USER-SELECTABLE LINKS EMBEDDED WITHIN THE COMMENTS PORTION OF A PROGRAM
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09828772
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Filing Dt:
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04/09/2001
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Title:
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BI-DIRECTIONAL ARCHITECTURE FOR A HIGH-VOLTAGE CROSS-COUPLED CHARGE PUMP
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09829510
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Filing Dt:
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04/09/2001
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Title:
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SRAM CELL DESIGN
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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09833307
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Filing Dt:
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04/11/2001
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Publication #:
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Pub Dt:
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04/25/2002
| | | | |
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Title:
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DUAL BIT ISOLATION SCHEME FOR FLASH MEMORY DEVICES HAVING POLYSILICON FLOATING GATES
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09834219
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Filing Dt:
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04/12/2001
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Title:
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I/O CELL ARCHITECTURE FOR CPLDS
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09836064
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04/16/2001
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Publication #:
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Pub Dt:
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09/20/2001
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Title:
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STEPPER ALIGNMENT MARK FORMATION WITH DUAL FIELD OXIDE PROCESS
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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09836065
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04/16/2001
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Publication #:
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Pub Dt:
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10/17/2002
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Title:
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SYSTEM AND METHOD FOR ERASE TEST OF INTEGRATED CIRCUIT DEVICE HAVING NON-HOMOGENEOUSLY SIZED SECTORS
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Patent #:
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Issue Dt:
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05/13/2003
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09842966
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Filing Dt:
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04/25/2001
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Title:
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PRECISION CRYSTAL OSCILLATOR CIRCUIT USED IN MICROCONTROLLER
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Patent #:
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Issue Dt:
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02/04/2003
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09844692
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04/27/2001
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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METHOD AND SYSTEM FOR REDUCING THINNING OF FIELD ISOLATION STRUCTURES IN A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09844785
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04/27/2001
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Title:
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MASTER/DUAL-SLAVE D TYPE FLIP-FLOP
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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09846146
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04/30/2001
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Title:
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CIRCUIT FOR CORRECTION OF DIFFERENTIAL SIGNAL PATH DELAYS IN A PLL
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09848568
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Filing Dt:
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05/02/2001
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Title:
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FLEXIBLE INPUT STRUCTURE FOR AN EMBEDDED MEMORY
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Patent #:
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Issue Dt:
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12/14/2004
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Application #:
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09849047
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05/04/2001
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Title:
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BURIED LAYER SUBSTRATE ISOLATION IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09849164
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05/04/2001
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Title:
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REDUCED STATIC PHASE ERROR CMOS PLL CHARGE PUMP
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Issue Dt:
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08/03/2004
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09849214
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05/04/2001
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Title:
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BIT INTERLEAVED DATA SERIAL INTERFACE
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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09850468
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05/07/2001
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Title:
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USB PERIPHERAL CONTAINING ITS OWN DEVICE DRIVER
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09855411
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05/15/2001
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Title:
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CURRENT STEERING REDUCED BITLINE VOLTAGE SWING, SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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09861026
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05/17/2001
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Title:
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METHOD FOR INTERFACING A SYNCHRONOUS MEMORY TO AN ASYNCHRONOUS MEMORY INTERFACE AND LOGIC OF SAME
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Patent #:
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NONE
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09864458
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Filing Dt:
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05/24/2001
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Publication #:
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Pub Dt:
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09/27/2001
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Title:
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Integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09867132
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05/29/2001
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Title:
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MOS OUTPUT DRIVER, AND CIRCUIT AND METHOD OF CONTROLLING SAME
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09873927
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06/04/2001
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Title:
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METHODS AND APPARATUS FOR READING A CAM CELL USING BOOSTED AND REGULATED GATE VOLTAGE
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09875708
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06/05/2001
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Title:
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METHOD AND AN APPARATUS FOR SYNTHESIZING A PROGRAMMABLE LOGIC CIRCUIT
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Patent #:
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Issue Dt:
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12/24/2002
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Application #:
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09877657
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06/07/2001
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Title:
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METASTABILITY RECOVERY CIRCUIT
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09877658
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Filing Dt:
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06/07/2001
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Title:
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DISCRIMINATOR CIRCUIT
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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09877659
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06/07/2001
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Title:
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METHOD AND APPARATUS FOR THE USE OF DISCRIMINATORS FOR PRIORITY ARBITRATION
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09877660
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06/07/2001
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Title:
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MULTIPORT ARBITRATION USING PHASED LOCKING ARBITERS
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09878433
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06/11/2001
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Publication #:
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Pub Dt:
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05/09/2002
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Title:
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RANDOM ACCESS MEMORY HAVING A READ/WRITE ADDRESS BUS AND PROCESS FOR WRITING TO AND READING FROM THE SAME
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09878434
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06/11/2001
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Publication #:
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Pub Dt:
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11/22/2001
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Title:
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RANDOM ACCESS MEMORY HAVING INDEPENDENT READ PORT AND WRITE PORT AND PROCESS FOR WRITING TO AND READING FROM THE SAME
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09878488
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06/11/2001
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Title:
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SYSTEM FOR RECONFIGURING A PERIPHERAL DEVICE BY DOWNLOADING INFORMATION FROM A HOST AND ELECTRONICALLY SIMULATING A PHYSICAL DISCONNECTION AND RECONNECTION TO RECONFIGURE THE DEVICE
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Issue Dt:
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08/20/2002
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09879738
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Filing Dt:
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06/12/2001
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Title:
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NOVEL RE-OXIDATION APPROACH TO IMPROVE PERIPHERAL GATE OXIDE INTEGRITY IN A TUNNEL NITRIDE OXIDATION PROCESS
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Issue Dt:
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10/22/2002
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09881354
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06/14/2001
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Title:
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OUTPUT BUFFER CROSSING POINT COMPENSATION
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Issue Dt:
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06/04/2002
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Application #:
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09882242
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06/15/2001
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Title:
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SPECIES IMPLANTATION FOR MINIMIZING INTERFACE DEFECT DENSITY IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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03/18/2003
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09882898
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06/15/2001
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Title:
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BLOCK REDUNDANCY IN ULTRA LOW POWER MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09884330
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Filing Dt:
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06/19/2001
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Title:
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METHOD OF PLACING DIE TO MINIMIZE DIE-TO-DIE ROUTING COMPLEXITY ON A SUBSTRATE
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09892189
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Filing Dt:
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06/26/2001
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Title:
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MODULATED CHARGE PUMP WHICH USES AN ANALOG TO DIGITAL CONVERTER TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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09893161
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Filing Dt:
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06/27/2001
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Title:
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ARCHITECTURE OF A PLL WITH DYNAMIC FREQUENCY CONTROL ON A PLD
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09894172
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Filing Dt:
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06/27/2001
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Title:
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COUNTER LOGIC FOR MULTIPLE MEMORY CONFIGURATION
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09894220
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Filing Dt:
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06/27/2001
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Title:
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METHOD TO IMPROVE ROUTABILITY IN PROGRAMMABLE LOGIC DEVICES VIA PRIORITIZED AUGMENTED FLOWS
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Patent #:
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Issue Dt:
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09/03/2002
|
Application #:
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09895305
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Filing Dt:
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06/30/2001
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Title:
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HIGH SPEED ASYNCHRONOUS AND PROGRAMMABLE STATE MACHINE FOR GENERATING ALMOST EMPTY SYNCHRONOUS FLAGS IN A SYNCHRONOUS FIFO
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Patent #:
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Issue Dt:
|
11/29/2005
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Application #:
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09895306
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Filing Dt:
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06/29/2001
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Title:
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HIGH SPEED ASYNCHRONOUS AND PROGRAMMABLE STATE MACHINE FOR GENERATING ALMOST FULL SYNCHRONOUS FLAGS IN A SYNCHRONOUS FIFO
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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09899871
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Filing Dt:
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07/06/2001
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Title:
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METHOD AND SYSTEM FOR CLEANING A POLISHING PAD
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Patent #:
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Issue Dt:
|
07/13/2004
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Application #:
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09902837
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Filing Dt:
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07/10/2001
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Title:
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METHOD AND SYSTEM FOR SPATIAL UNIFORM POLISHING
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Patent #:
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Issue Dt:
|
08/23/2005
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Application #:
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09904042
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Filing Dt:
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07/11/2001
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Title:
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RECESSED TUNNEL OXIDE PROFILE FOR IMPROVED RELIABILITY IN NAND DEVICES
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Patent #:
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Issue Dt:
|
12/23/2003
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Application #:
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09904745
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Filing Dt:
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07/13/2001
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Title:
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METHOD FOR TRANSFERRING A PLURALITY OF INTEGRATED CIRCUIT DEVICES INTO AND/OR OUT OF A PLURALITY OF SOCKETS
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Patent #:
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Issue Dt:
|
03/28/2006
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Application #:
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09904750
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Filing Dt:
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07/13/2001
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Title:
|
PROGRAMMABLE SERIAL INTERFACE
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Patent #:
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Issue Dt:
|
03/18/2003
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Application #:
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09905421
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Filing Dt:
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07/13/2001
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Publication #:
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Pub Dt:
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11/08/2001
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Title:
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MIXED MODE MULTI LEVEL MODE INDICTOR
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Patent #:
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Issue Dt:
|
08/05/2003
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Application #:
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09909109
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Filing Dt:
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07/18/2001
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Title:
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CONFIGURING DIGITAL FUNCTIONS IN A DIGITAL CONFIGURABLE MACRO ARCHITECTURE
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Patent #:
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Issue Dt:
|
02/28/2006
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Application #:
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09912768
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Filing Dt:
|
07/24/2001
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Title:
|
Dual mode relaxation oscillator generating a clock signal operating at a frequency substantially same in both first and second power modes
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Patent #:
|
NONE
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Issue Dt:
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Application #:
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09912833
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Filing Dt:
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07/25/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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Technique for guaranteeing the availability of per thread storage in a distributed computing environment
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Patent #:
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Issue Dt:
|
12/16/2003
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Application #:
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09912834
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Filing Dt:
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07/25/2001
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Publication #:
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Pub Dt:
|
03/14/2002
| | | | |
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Title:
|
MULTIPLE BLOCK SEQUENTIAL MEMORY MANAGEMENT
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Patent #:
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NONE
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Issue Dt:
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Application #:
|
09912856
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Filing Dt:
|
07/25/2001
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Publication #:
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Pub Dt:
|
03/07/2002
| | | | |
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Title:
|
High availability shared memory system
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|
|
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Patent #:
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|
Issue Dt:
|
08/24/2004
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Application #:
|
09912870
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Filing Dt:
|
07/25/2001
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|
Publication #:
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Pub Dt:
|
02/07/2002
| | | | |
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Title:
|
RESOURCE LOCKING AND THREAD SYNCHRONIZATION IN A MULTIPROCESSOR ENVIRONMENT
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|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
09912872
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Filing Dt:
|
07/25/2001
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|
Publication #:
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Pub Dt:
|
03/14/2002
| | | | |
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Title:
|
Distributed shared memory management
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
09912898
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Filing Dt:
|
07/25/2001
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|
Publication #:
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Pub Dt:
|
02/07/2002
| | | | |
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Title:
|
METHODS AND SYSTEMS FOR A SHARED MEMORY UNIT WITH EXTENDABLE FUNCTIONS
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|
|
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Patent #:
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Issue Dt:
|
01/06/2004
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Application #:
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09912954
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Filing Dt:
|
07/25/2001
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Publication #:
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Pub Dt:
|
02/07/2002
| | | | |
|
Title:
|
DEMAND USABLE ADAPTER MEMORY ACCESS MANAGEMENT
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
09915002
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Filing Dt:
|
07/25/2001
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|
Publication #:
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Pub Dt:
|
01/31/2002
| | | | |
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Title:
|
Shared as needed programming model
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09915018
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Filing Dt:
|
07/25/2001
|
|
Publication #:
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Pub Dt:
|
01/30/2003
| | | | |
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Title:
|
VOLTAGE BOOST CIRCUIT USING SUPPLY VOLTAGE DETECTION TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS IN READ MODE VOLTAGES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
09915109
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Filing Dt:
|
07/25/2001
|
|
Publication #:
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Pub Dt:
|
01/31/2002
| | | | |
|
Title:
|
LOAD/STORE MICROPACKET HANDLING SYSTEM
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/13/2005
|
Application #:
|
09915794
|
Filing Dt:
|
07/26/2001
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|
Title:
|
ARCHITECTURE THAT CONVERTS A HALF-DUPLEX BUS TO A FULL-DUPLEX BUS WHILE KEEPING THE BANDWIDTH OF THE BUS CONSTANT
|
|
|
|
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Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09915823
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Filing Dt:
|
07/26/2001
|
|
Title:
|
BUFFER WITH STABLE TRIP POINT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
09916453
|
Filing Dt:
|
07/27/2001
|
|
Title:
|
TECHNIQUES FOR JEDEC FILE INFORMATION INTEGRITY AND PRESERVATION OF DEVICE PROGRAMMING SPECIFICATIONS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09916978
|
Filing Dt:
|
07/27/2001
|
|
Title:
|
SIGNAL SCALING SCHEME FOR A DELTA SIGMA MODULATOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09917178
|
Filing Dt:
|
07/30/2001
|
|
Title:
|
NOR ARRAY WITH BURIED TRENCH SOURCE LINE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
09917440
|
Filing Dt:
|
07/27/2001
|
|
Title:
|
N-GATE/N-SUBSTRATE OR P-GATE/P-SUBSTRATE CAPACITOR TO CHARACTERIZE POLYSILICON GATE DEPLETION EVALUATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09918583
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Filing Dt:
|
07/31/2001
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2003
| | | | |
|
Title:
|
DIGITALLY CONTROLLED ANALOG DELAY LOCKED LOOP (DLL)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2005
|
Application #:
|
09920374
|
Filing Dt:
|
07/31/2001
|
|
Title:
|
RETICLE REPEATER MONITOR WAFER AND METHOD FOR VERIFYING RETICLES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2003
|
Application #:
|
09922419
|
Filing Dt:
|
08/03/2001
|
|
Title:
|
POWER SUPPLY PUMP CIRCUIT FOR A MICROCONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
09922579
|
Filing Dt:
|
08/03/2001
|
|
Title:
|
METHOD FOR EFFICIENT SUPPLY OF POWER TO A MICROCONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2002
|
Application #:
|
09922764
|
Filing Dt:
|
08/07/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/01/2002
| | | | |
|
Title:
|
CURRENT PULSE RECEIVING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2002
|
Application #:
|
09925205
|
Filing Dt:
|
08/08/2001
|
|
Publication #:
|
|
Pub Dt:
|
03/07/2002
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR ETCHING TUNNEL OXIDE TO REDUCE UNDERCUTTING DURING MEMORY ARRAY FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2004
|
Application #:
|
09927134
|
Filing Dt:
|
08/10/2001
|
|
Title:
|
PROCESS FOR TREATING ONO DIELECTRIC FILM OF A FLOATING GATE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
09927863
|
Filing Dt:
|
08/10/2001
|
|
Title:
|
METHODS OF FORMING SEMICONDUCTOR STRUCTURES HAVING REDUCED DEFECTS, AND ARTICLES AND DEVICES FORMED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2003
|
Application #:
|
09928059
|
Filing Dt:
|
08/10/2001
|
|
Title:
|
DECODER APPARATUS AND METHODS FOR PRE-CHARGING BIT LINES
|
|
