Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 042198/0238 | |
| Pages: | 5 |
| | Recorded: | 05/01/2017 | | |
| Attorney Dkt #: | PJCT-2016-0043-ASSGN-AHC |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09903303
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Filing Dt:
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07/10/2001
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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Compact layout for a semiconductor device
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10004976
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Filing Dt:
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12/03/2001
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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INTEGRATED CIRCUITS WITH SCALABLE DESIGN
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10024943
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Filing Dt:
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12/18/2001
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Publication #:
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Pub Dt:
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06/19/2003
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Title:
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DYNAMIC MATCHING IN CASCODE CIRCUITS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10025437
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Filing Dt:
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12/18/2001
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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Internal impedance match in integrated circuits
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Patent #:
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Issue Dt:
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02/15/2005
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Application #:
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10327512
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Filing Dt:
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12/19/2002
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Publication #:
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Pub Dt:
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11/20/2003
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Title:
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COMPACT LAYOUT FOR A SEMICONDUCTOR DEVICE
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Assignee
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| 20 SYLVAN ROAD |
| WOBURN, MASSACHUSETTS 01801 |
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Correspondence name and address
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DONALD BOLLELLA
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5221 CALIFORNIA AVENUE, 21-1
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IRVINE, CA 92617
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