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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:056510/0240   Pages: 7
Recorded: 06/02/2021
Attorney Dkt #:VARIOUS
Conveyance: MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 94
1
Patent #:
Issue Dt:
04/10/2007
Application #:
10504217
Filing Dt:
08/10/2004
Publication #:
Pub Dt:
06/16/2005
Title:
RETIMING CIRCUITS USING A CUT-BASED APPROACH
2
Patent #:
Issue Dt:
04/03/2007
Application #:
10749283
Filing Dt:
12/30/2003
Publication #:
Pub Dt:
10/21/2004
Title:
BUILT-IN SELF-ANALYZER FOR EMBEDDED MEMORY
3
Patent #:
Issue Dt:
05/06/2008
Application #:
10778950
Filing Dt:
02/13/2004
Publication #:
Pub Dt:
11/18/2004
Title:
COMPRESSING TEST RESPONSES USING A COMPACTOR
4
Patent #:
Issue Dt:
07/31/2007
Application #:
10785608
Filing Dt:
02/23/2004
Publication #:
Pub Dt:
05/05/2005
Title:
MEMORY RE-IMPLEMENTATION FOR FIELD PROGRAMMABLE GATE ARRAYS
5
Patent #:
Issue Dt:
09/25/2007
Application #:
10846739
Filing Dt:
05/14/2004
Publication #:
Pub Dt:
12/30/2004
Title:
CONFIGURABLE ADVANCED TECHNOLOGY ATTACHEMENT/INTEGRATED DRIVE ELECTRONICS HOST CONTROLLER WITH PROGRAMMABLE TIMING REGISTERS THAT STORE TIMING PARAMETERS THAT CONTROL COMMUNICATIONS
6
Patent #:
Issue Dt:
04/27/2010
Application #:
10856425
Filing Dt:
05/27/2004
Publication #:
Pub Dt:
12/30/2004
Title:
OSCULATING MODELS FOR PREDICTING THE OPERATION OF A CIRCUIT STRUCTURE
7
Patent #:
Issue Dt:
05/12/2009
Application #:
10861851
Filing Dt:
06/04/2004
Publication #:
Pub Dt:
09/15/2005
Title:
TESTING MEMORIES USING ALGORITHM SELECTION
8
Patent #:
Issue Dt:
05/22/2007
Application #:
10895485
Filing Dt:
07/20/2004
Publication #:
Pub Dt:
03/31/2005
Title:
SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION
9
Patent #:
Issue Dt:
07/03/2007
Application #:
10925230
Filing Dt:
08/23/2004
Publication #:
Pub Dt:
10/06/2005
Title:
COMPACTOR INDEPENDENT FAULT DIAGNOSIS
10
Patent #:
Issue Dt:
06/19/2007
Application #:
10956983
Filing Dt:
09/30/2004
Publication #:
Pub Dt:
04/14/2005
Title:
RESOURCE MANAGEMENT DURING SYSTEM VERIFICATION
11
Patent #:
Issue Dt:
11/13/2007
Application #:
10961760
Filing Dt:
10/07/2004
Publication #:
Pub Dt:
04/14/2005
Title:
USING CONSTRAINED SCAN CELLS TO TEST INTEGRATED CIRCUITS
12
Patent #:
Issue Dt:
02/24/2009
Application #:
10972025
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
06/02/2005
Title:
MUTUAL INDUCTANCE EXTRACTION USING DIPOLE APPROXIMATIONS
13
Patent #:
Issue Dt:
03/04/2008
Application #:
10975717
Filing Dt:
10/26/2004
Publication #:
Pub Dt:
02/02/2006
Title:
TEST STRUCTURES AND METHOD FOR INTERCONNECT IMPEDANCE PROPERTY EXTRACTION
14
Patent #:
Issue Dt:
03/24/2009
Application #:
10979496
Filing Dt:
11/01/2004
Publication #:
Pub Dt:
10/27/2005
Title:
GENERATING TEST PATTERNS HAVING ENHANCED COVERAGE OF UNTARGETED DEFECTS
15
Patent #:
Issue Dt:
08/12/2008
Application #:
10985398
Filing Dt:
11/10/2004
Publication #:
Pub Dt:
12/01/2005
Title:
LOOP MANIPULATION IN A BEHAVIORAL SYNTHESIS TOOL
16
Patent #:
Issue Dt:
03/13/2007
Application #:
11015295
Filing Dt:
12/17/2004
Publication #:
Pub Dt:
11/03/2005
Title:
COMBINED HOST INTERFACE CONTROLLER FOR CONDUCTING COMMUNICATION BETWEEN A HOST SYSTEM AND MULTIPLE DEVICES IN MULTIPLE PROTOCOLS
17
Patent #:
Issue Dt:
07/17/2007
Application #:
11041459
Filing Dt:
01/21/2005
Publication #:
Pub Dt:
08/04/2005
Title:
SOURCE OPTIMIZATION FOR IMAGE FIDELITY AND THROUGHPUT
18
Patent #:
Issue Dt:
05/19/2009
Application #:
11062513
Filing Dt:
07/26/2004
Publication #:
Pub Dt:
12/22/2005
Title:
OPC SIMULATION MODEL USING SOCS DECOMPOSITION OF EDGE FRAGMENTS
19
Patent #:
Issue Dt:
06/19/2007
Application #:
11066597
Filing Dt:
02/24/2005
Publication #:
Pub Dt:
09/29/2005
Title:
LONG RANGE CORRECTIONS IN INTEGRATED CIRCUIT LAYOUT DESIGNS
20
Patent #:
Issue Dt:
11/18/2008
Application #:
11068036
Filing Dt:
03/01/2005
Publication #:
Pub Dt:
06/08/2006
Title:
ACYCLIC MODELING OF COMBINATIONAL LOOPS
21
Patent #:
Issue Dt:
08/10/2010
Application #:
11102596
Filing Dt:
04/07/2005
Publication #:
Pub Dt:
02/09/2006
Title:
BRANCH MERGE REDUCTION OF RLCM NETWORKS
22
Patent #:
Issue Dt:
08/05/2014
Application #:
11123340
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
11/10/2005
Title:
INTEGRATED CIRCUIT LAYOUT DESIGN METHODOLOGY WITH PROCESS VARIATION BANDS
23
Patent #:
Issue Dt:
04/08/2008
Application #:
11140678
Filing Dt:
05/27/2005
Publication #:
Pub Dt:
12/01/2005
Title:
METASTABILITY EFFECTS SIMULATION FOR A CIRCUIT DESCRIPTION
24
Patent #:
Issue Dt:
02/17/2009
Application #:
11144157
Filing Dt:
06/02/2005
Publication #:
Pub Dt:
09/07/2006
Title:
CHROMELESS PHASE SHIFTING MASK FOR INTEGRATED CIRCUITS USING INTERIOR REGION
25
Patent #:
Issue Dt:
12/06/2011
Application #:
11176002
Filing Dt:
07/06/2005
Publication #:
Pub Dt:
02/16/2006
Title:
MANAGING COMMUNICATION BANDWIDTH IN CO-VERIFICATION OF CIRCUIT DESIGNS
26
Patent #:
Issue Dt:
01/20/2009
Application #:
11181036
Filing Dt:
07/12/2005
Publication #:
Pub Dt:
04/06/2006
Title:
SOFTWARE STATE REPLAY
27
Patent #:
Issue Dt:
05/25/2010
Application #:
11242633
Filing Dt:
10/03/2005
Publication #:
Pub Dt:
06/21/2007
Title:
FEATURE FAILURE CORRELATION
28
Patent #:
Issue Dt:
07/01/2008
Application #:
11258769
Filing Dt:
10/25/2005
Publication #:
Pub Dt:
07/13/2006
Title:
REMOVING THE EFFECTS OF UNKNOWN TEST VALUES FROM COMPACTED TEST RESPONSES
29
Patent #:
Issue Dt:
10/07/2008
Application #:
11282938
Filing Dt:
11/18/2005
Publication #:
Pub Dt:
07/13/2006
Title:
FLEXIBLE MEMORY BUILT-IN-SELF-TEST (MBIST) METHOD AND APPARATUS
30
Patent #:
Issue Dt:
02/03/2009
Application #:
11305849
Filing Dt:
12/16/2005
Publication #:
Pub Dt:
01/11/2007
Title:
REDUCED-PIN-COUNT-TESTING ARCHITECTURES FOR APPLYING TEST PATTERNS
31
Patent #:
Issue Dt:
02/03/2009
Application #:
11364802
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
11/30/2006
Title:
CALCULATION SYSTEM FOR INVERSE MASKS
32
Patent #:
Issue Dt:
06/08/2010
Application #:
11452677
Filing Dt:
06/13/2006
Publication #:
Pub Dt:
08/09/2007
Title:
MANAGING AND CONTROLLING THE USE OF HARDWARE RESOURCES ON INTEGRATED CIRCUITS
33
Patent #:
Issue Dt:
06/30/2009
Application #:
11478120
Filing Dt:
06/28/2006
Publication #:
Pub Dt:
01/11/2007
Title:
GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT WITH TIMING EXCEPTION PATHS
34
Patent #:
Issue Dt:
03/24/2009
Application #:
11497977
Filing Dt:
08/01/2006
Publication #:
Pub Dt:
02/15/2007
Title:
DIRECT LOGIC DIAGNOSTICS WITH SIGNATURE-BASED FAULT DICTIONARIES
35
Patent #:
Issue Dt:
08/11/2009
Application #:
11499036
Filing Dt:
08/04/2006
Publication #:
Pub Dt:
02/22/2007
Title:
AUTOMATING POWER DOMAINS IN ELECTRONIC DESIGN AUTOMATION
36
Patent #:
Issue Dt:
11/23/2010
Application #:
11510079
Filing Dt:
08/25/2006
Publication #:
Pub Dt:
09/20/2007
Title:
ENHANCED DIAGNOSIS WITH LIMITED FAILURE CYCLES
37
Patent #:
Issue Dt:
04/17/2012
Application #:
11580650
Filing Dt:
10/13/2006
Publication #:
Pub Dt:
05/17/2007
Title:
MODULAR COMPACTION OF TEST RESPONSES
38
Patent #:
Issue Dt:
05/27/2008
Application #:
11606769
Filing Dt:
11/29/2006
Publication #:
Pub Dt:
08/23/2007
Title:
GRID-BASED RESIST SIMULATION
39
Patent #:
Issue Dt:
05/04/2010
Application #:
11613118
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
08/23/2007
Title:
COMPUTATION OF ELECTRICAL PROPERTIES OF AN IC LAYOUT
40
Patent #:
Issue Dt:
01/04/2011
Application #:
11626307
Filing Dt:
01/23/2007
Publication #:
Pub Dt:
05/24/2007
Title:
OPC CONFLICT IDENTIFICATION AND EDGE PRIORITY SYSTEM
41
Patent #:
Issue Dt:
06/30/2009
Application #:
11677044
Filing Dt:
02/20/2007
Publication #:
Pub Dt:
07/05/2007
Title:
SELECTIVELY REDUCING THE NUMBER OF CELL EVALUATIONS IN A HARDWARE SIMULATION
42
Patent #:
Issue Dt:
12/11/2012
Application #:
11682089
Filing Dt:
03/05/2007
Publication #:
Pub Dt:
09/06/2007
Title:
MODELING OF SYSTEMS USING CANONICAL FORM FUNCTIONS AND SYMBOLIC REGRESSION
43
Patent #:
Issue Dt:
08/19/2014
Application #:
11688782
Filing Dt:
03/20/2007
Publication #:
Pub Dt:
09/27/2007
Title:
SPEEDING UP DEFECT DIAGNOSIS TECHNIQUES
44
Patent #:
Issue Dt:
11/18/2008
Application #:
11704470
Filing Dt:
02/08/2007
Publication #:
Pub Dt:
09/27/2007
Title:
EXTRACTING HIGH FREQUENCY IMPEDANCE IN A CIRCUIT DESIGN USING BROADBAND REPRESENTATIONS
45
Patent #:
Issue Dt:
11/16/2010
Application #:
11715667
Filing Dt:
03/08/2007
Publication #:
Pub Dt:
09/20/2007
Title:
SUM OF COHERENT SYSTEMS (SOCS) APPROXIMATION BASED ON OBJECT INFORMATION
46
Patent #:
Issue Dt:
07/20/2010
Application #:
11780039
Filing Dt:
07/19/2007
Publication #:
Pub Dt:
01/24/2008
Title:
INTERACTIVE SCHEMATIC FOR USE IN ANALOG, MIXED-SIGNAL, AND CUSTOM DIGITAL CIRCUIT DESIGN
47
Patent #:
Issue Dt:
03/30/2010
Application #:
11780085
Filing Dt:
07/19/2007
Publication #:
Pub Dt:
01/24/2008
Title:
SYSTEM AND METHOD FOR DETERMINING AND VISUALIZING TRADEOFFS BETWEEN YIELD AND PERFORMANCE IN ELECTRICAL CIRCUIT DESIGNS
48
Patent #:
Issue Dt:
04/27/2010
Application #:
11780744
Filing Dt:
07/20/2007
Publication #:
Pub Dt:
01/24/2008
Title:
DATA-MINING-BASED KNOWLEDGE EXTRACTION AND VISUALIZATION OF ANALOG/ MIXED-SIGNAL/ CUSTOM DIGITAL CIRCUIT DESIGN FLOW
49
Patent #:
Issue Dt:
03/23/2010
Application #:
11784460
Filing Dt:
04/05/2007
Publication #:
Pub Dt:
10/25/2007
Title:
TEST GENERATION METHODS FOR REDUCING POWER DISSIPATION AND SUPPLY CURRENTS
50
Patent #:
Issue Dt:
11/01/2011
Application #:
11796374
Filing Dt:
04/27/2007
Publication #:
Pub Dt:
12/13/2007
Title:
TIMING-AWARE TEST GENERATION AND FAULT SIMULATION
51
Patent #:
Issue Dt:
05/25/2010
Application #:
11818110
Filing Dt:
06/12/2007
Publication #:
Pub Dt:
11/01/2007
Title:
CONVERSION OF A THREE-DIMENSIONAL WIRE HARNESS REPRESENTATIVE TO A TWO-DIMENSIONAL ORTHOGONAL WIRE HARNESS REPRESENTATIVE
52
Patent #:
Issue Dt:
08/31/2010
Application #:
11838858
Filing Dt:
08/14/2007
Publication #:
Pub Dt:
02/14/2008
Title:
DIAGNOSING MIXED SCAN CHAIN AND SYSTEM LOGIC DEFECTS
53
Patent #:
Issue Dt:
01/26/2010
Application #:
11840122
Filing Dt:
08/16/2007
Publication #:
Pub Dt:
11/20/2008
Title:
CROSSLINKING OF NETLISTS
54
Patent #:
Issue Dt:
08/03/2010
Application #:
11845327
Filing Dt:
08/27/2007
Publication #:
Pub Dt:
10/30/2008
Title:
DRAM WITH WORD LINE COMPENSATION
55
Patent #:
Issue Dt:
11/16/2010
Application #:
11876430
Filing Dt:
10/22/2007
Publication #:
Pub Dt:
05/15/2008
Title:
DEFECT LOCALIZATION BASED ON DEFECTIVE CELL DIAGNOSIS
56
Patent #:
Issue Dt:
09/14/2010
Application #:
11880373
Filing Dt:
07/19/2007
Publication #:
Pub Dt:
02/28/2008
Title:
LOW POWER DECOMPRESSION OF TEST CUBES
57
Patent #:
Issue Dt:
11/08/2011
Application #:
11937423
Filing Dt:
11/08/2007
Publication #:
Pub Dt:
06/12/2008
Title:
ANALYSIS OPTIMIZER
58
Patent #:
Issue Dt:
11/23/2010
Application #:
11973084
Filing Dt:
10/05/2007
Publication #:
Pub Dt:
09/25/2008
Title:
BUILT-IN SELF-TEST OF INTEGRATED CIRCUITS USING SELECTABLE WEIGHTING OF TEST PATTERNS
59
Patent #:
Issue Dt:
12/17/2013
Application #:
11986564
Filing Dt:
11/20/2007
Publication #:
Pub Dt:
08/07/2008
Title:
MODEL-BASED DESIGN VERIFICATION
60
Patent #:
Issue Dt:
05/04/2010
Application #:
12016602
Filing Dt:
01/18/2008
Publication #:
Pub Dt:
06/05/2008
Title:
RAM WITH TRIM CAPACITORS
61
Patent #:
Issue Dt:
06/15/2010
Application #:
12016738
Filing Dt:
01/18/2008
Publication #:
Pub Dt:
09/18/2008
Title:
MEMORY ROW AND COLUMN REDUNDANCY
62
Patent #:
Issue Dt:
08/19/2008
Application #:
12019852
Filing Dt:
01/25/2008
Publication #:
Pub Dt:
06/12/2008
Title:
LOW-POWER CAM CELL
63
Patent #:
Issue Dt:
04/12/2011
Application #:
12039720
Filing Dt:
02/28/2008
Publication #:
Pub Dt:
12/04/2008
Title:
SELECTIVE OPTICAL PROXIMITY LAYOUT DESIGN DATA CORRECTION
64
Patent #:
Issue Dt:
04/12/2011
Application #:
12069752
Filing Dt:
02/12/2008
Publication #:
Pub Dt:
08/14/2008
Title:
LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS
65
Patent #:
Issue Dt:
09/04/2012
Application #:
12074162
Filing Dt:
02/29/2008
Publication #:
Pub Dt:
09/04/2008
Title:
GENERATING TEST SETS FOR DIAGNOSING SCAN CHAIN FAILURES
66
Patent #:
Issue Dt:
02/23/2010
Application #:
12117701
Filing Dt:
05/08/2008
Publication #:
Pub Dt:
09/04/2008
Title:
METHODS FOR DISTRIBUTING PROGRAMS FOR GENERATING TEST DATA
67
Patent #:
Issue Dt:
11/19/2013
Application #:
12131294
Filing Dt:
06/02/2008
Publication #:
Pub Dt:
12/04/2008
Title:
ON-THE-FLY IMPROVEMENT OF CERTAINTY OF STATISTICAL ESTIMATES IN STATISTICAL DESIGN, WITH CORRESPONDING VISUAL FEEDBACK
68
Patent #:
Issue Dt:
09/20/2011
Application #:
12151074
Filing Dt:
05/02/2008
Publication #:
Pub Dt:
11/06/2008
Title:
MODELING THE SKIN EFFECT USING EFFICIENT CONDUCTION MODE TECHNIQUES
69
Patent #:
Issue Dt:
01/28/2014
Application #:
12183046
Filing Dt:
07/30/2008
Publication #:
Pub Dt:
05/14/2009
Title:
FORMING SEPARATION DIRECTIVES USING A PRINTING FEASIBILITY ANALYSIS
70
Patent #:
Issue Dt:
01/17/2012
Application #:
12184089
Filing Dt:
07/31/2008
Publication #:
Pub Dt:
04/30/2009
Title:
MODEL BASED MICRODEVICE DESIGN LAYOUT CORRECTION
71
Patent #:
Issue Dt:
08/23/2011
Application #:
12237069
Filing Dt:
09/24/2008
Publication #:
Pub Dt:
03/26/2009
Title:
MODEL-BUILDING OPTIMIZATION
72
Patent #:
Issue Dt:
12/27/2011
Application #:
12265693
Filing Dt:
11/05/2008
Publication #:
Pub Dt:
10/08/2009
Title:
ACCURATELY IDENTIFYING FAILING SCAN BITS IN COMPRESSION ENVIRONMENTS
73
Patent #:
Issue Dt:
10/15/2013
Application #:
12330506
Filing Dt:
12/08/2008
Publication #:
Pub Dt:
11/05/2009
Title:
SEGMENTING INTEGRATED CIRCUIT LAYOUT DESIGN FILES USING SPECULATIVE PARSING
74
Patent #:
Issue Dt:
04/24/2012
Application #:
12341996
Filing Dt:
12/22/2008
Publication #:
Pub Dt:
12/03/2009
Title:
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
75
Patent #:
Issue Dt:
11/15/2011
Application #:
12343415
Filing Dt:
12/23/2008
Publication #:
Pub Dt:
06/04/2009
Title:
CLOCK MODEL FOR FORMAL VERIFICATION OF A DIGITAL CIRCUIT DESCRIPTION
76
Patent #:
Issue Dt:
05/29/2012
Application #:
12353834
Filing Dt:
01/14/2009
Publication #:
Pub Dt:
09/24/2009
Title:
SITE SELECTIVE OPTICAL PROXIMITY CORRECTION
77
Patent #:
Issue Dt:
01/03/2012
Application #:
12353856
Filing Dt:
01/14/2009
Publication #:
Pub Dt:
07/30/2009
Title:
DIRECT REGISTER ACCESS FOR HOST SIMULATION
78
Patent #:
Issue Dt:
05/22/2012
Application #:
12406820
Filing Dt:
03/18/2009
Publication #:
Pub Dt:
07/09/2009
Title:
PRE-BIAS OPTICAL PROXIMITY CORRECTION
79
Patent #:
Issue Dt:
11/20/2012
Application #:
12471227
Filing Dt:
05/22/2009
Publication #:
Pub Dt:
09/17/2009
Title:
TEST PATTERN GENERATION FOR DIAGNOSING SCAN CHAIN FAILURES
80
Patent #:
Issue Dt:
08/26/2014
Application #:
12615184
Filing Dt:
11/09/2009
Publication #:
Pub Dt:
09/23/2010
Title:
Hierarchical Verification Of Clock Domain Crossings
81
Patent #:
Issue Dt:
08/20/2013
Application #:
12622114
Filing Dt:
11/19/2009
Publication #:
Pub Dt:
08/26/2010
Title:
MASK MODEL CALIBRATION TECHNOLOGIES INVOLVING ETCH EFFECT AND EXPOSURE EFFECT
82
Patent #:
Issue Dt:
06/11/2013
Application #:
12625466
Filing Dt:
11/24/2009
Publication #:
Pub Dt:
10/21/2010
Title:
ELECTRON BEAM SIMULATION CORNER CORRECTION FOR OPTICAL LITHPOGRAPHY
83
Patent #:
Issue Dt:
04/16/2013
Application #:
12629036
Filing Dt:
12/01/2009
Publication #:
Pub Dt:
02/24/2011
Title:
On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis
84
Patent #:
Issue Dt:
06/18/2013
Application #:
12634682
Filing Dt:
12/09/2009
Publication #:
Pub Dt:
07/22/2010
Title:
SPEED-PATH DEBUG USING AT-SPEED SCAN TEST PATTERNS
85
Patent #:
Issue Dt:
07/17/2012
Application #:
12719981
Filing Dt:
03/09/2010
Publication #:
Pub Dt:
06/24/2010
Title:
LOGIC INJECTION
86
Patent #:
Issue Dt:
09/18/2012
Application #:
12776933
Filing Dt:
05/10/2010
Publication #:
Pub Dt:
09/02/2010
Title:
COMBINATION OF GROUND DEVICES IN WIRING HARNESS DESIGNS
87
Patent #:
Issue Dt:
09/04/2012
Application #:
12854747
Filing Dt:
08/11/2010
Publication #:
Pub Dt:
12/02/2010
Title:
RANDOM ACCESS MEMORY FOR USE IN AN EMULATION ENVIRONMENT
88
Patent #:
Issue Dt:
12/27/2011
Application #:
12858430
Filing Dt:
08/17/2010
Publication #:
Pub Dt:
12/09/2010
Title:
DUAL METRIC OPC
89
Patent #:
Issue Dt:
07/08/2014
Application #:
13160173
Filing Dt:
06/14/2011
Publication #:
Pub Dt:
10/13/2011
Title:
SELECTIVE SHIELDING FOR MULTIPLE EXPOSURE MASKS
90
Patent #:
Issue Dt:
06/25/2013
Application #:
13185263
Filing Dt:
07/18/2011
Publication #:
Pub Dt:
01/12/2012
Title:
FAULT SUPPORT IN AN EMULATION ENVIRONMENT
91
Patent #:
Issue Dt:
04/12/2016
Application #:
13274276
Filing Dt:
10/14/2011
Publication #:
Pub Dt:
09/20/2012
Title:
MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS
92
Patent #:
Issue Dt:
04/26/2016
Application #:
13330618
Filing Dt:
12/19/2011
Publication #:
Pub Dt:
06/28/2012
Title:
MODELLING AND SIMULATION METHOD
93
Patent #:
Issue Dt:
03/04/2014
Application #:
13487542
Filing Dt:
06/04/2012
Publication #:
Pub Dt:
11/08/2012
Title:
RESOURCE REMAPPING IN A HARDWARE EMULATION ENVIRONMENT
94
Patent #:
Issue Dt:
11/22/2016
Application #:
14517609
Filing Dt:
10/17/2014
Publication #:
Pub Dt:
02/05/2015
Title:
IDENTIFICATION OF POWER SENSITIVE SCAN CELLS
Assignor
1
Exec Dt:
12/30/2020
Newly Merged Entity Data
1
Exec Dt:
12/30/2020
Newly Merged Entity's New Name
1
5800 GRANITE PARKWAY, SUITE 600
PLANO, TEXAS 75024
Correspondence name and address
SIEMENS CORPORATION IP DEPT - MAIL CODE INT-244
3850 QUADRANGLE BOULEVARD
ORLANDO, FL 32817

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