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Total properties:
19
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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09243977
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Filing Dt:
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02/04/1999
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Title:
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IMPLEMENTATION OF EEPROM USING INTERMEDIATE GATE VOLTAGE TO AVOID DISTURB CONDITIONS
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09244318
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Filing Dt:
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02/04/1999
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Title:
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MULTI-STAGE CHARGE PUMP HAVING HIGH-VOLTAGE PUMP CONTROL FEEDBACK AND METHOD OF OPERATING SAME
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09295934
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Filing Dt:
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04/21/1999
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Title:
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METHOD AND STRUCTURE FOR ACCESSING A REDUCED ADDRESS SPACE OF A DEFECTIVE MEMORY
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09542501
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Filing Dt:
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04/03/2000
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Title:
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Triple layer pre-metal dielectric structure for CMOS memory devices
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09888348
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Filing Dt:
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06/21/2001
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Title:
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SENSE AMPLIFIER OFFSET CANCELLATION IN NON-VOLTAGE MEMORY CIRCUITS BY DEDICATED PROGRAMMED REFERENCE NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09888353
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Filing Dt:
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06/21/2001
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Title:
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HIGH VOLTAGE CHARGE PUMP FOR PROVIDING OUTPUT VOLTAGE CLOSE TO MAXIMUM HIGH VOLTAGE OF A CMOS
DEVICE
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09898725
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Filing Dt:
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07/03/2001
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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METHOD AND APPARATUS FOR REDUCING THE NUMBER OF PROGRAMMED BITS IN A MEMORY ARRAY
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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09931848
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Filing Dt:
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08/16/2001
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Publication #:
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Pub Dt:
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02/20/2003
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Title:
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NON-VOLATILE MEMORY DEVICE WITH SELF TEST
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09935013
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Filing Dt:
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08/21/2001
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Title:
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STRUCTURE AND METHOD FOR HIGH SPEED SENSING OF MEMORY ARRAYS
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09941451
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Filing Dt:
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08/28/2001
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Title:
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VOLTAGE REGULATOR FOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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09975064
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Filing Dt:
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10/10/2001
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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EFFICIENT TEST STRUCTURE FOR NON-VOLATILE MEMORY AND OTHER SEMICONDUCTOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10043677
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Filing Dt:
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01/09/2002
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Title:
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MULTI-BIT PROGRAMMABLE MEMORY CELL HAVING MULTIPLE ANTI-FUSE ELEMENTS
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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10154395
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Filing Dt:
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05/23/2002
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Publication #:
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Pub Dt:
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11/27/2003
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Title:
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SELF-ALIGNED PROCESS FOR FABRICATING MEMORY CELLS WITH TWO ISOLATED FLOATING GATES
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10228452
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Filing Dt:
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08/26/2002
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Publication #:
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Pub Dt:
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02/26/2004
| | | | |
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Title:
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VOLTAGE CONTROL CIRCUIT FOR HIGH VOLTAGE SUPPLY
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10282856
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Filing Dt:
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10/28/2002
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Publication #:
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Pub Dt:
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04/29/2004
| | | | |
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Title:
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COMPLEMENTARY NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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04/12/2005
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Application #:
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10393958
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Filing Dt:
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03/20/2003
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Publication #:
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Pub Dt:
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09/23/2004
| | | | |
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Title:
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TRIPLE-WELL CHARGE PUMP STAGE WITH NO THRESHOLD VOLTAGE BACK-BIAS EFFECT
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10430931
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Filing Dt:
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05/06/2003
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
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Title:
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MULTI-BIT PROGRAMMABLE MEMORY CELL HAVING MULTIPLE ANTI-FUSE ELEMENTS
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Patent #:
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Issue Dt:
|
08/10/2004
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Application #:
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10613845
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Filing Dt:
|
07/03/2003
|
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Title:
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LOW VOLTAGE SENSING CIRCUIT FOR NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
|
03/04/2008
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Application #:
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11277592
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Filing Dt:
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03/27/2006
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Publication #:
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Pub Dt:
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09/27/2007
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Title:
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ULTRA LOW POWER NON-VOLATILE MEMORY MODULE
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