Patent Assignment Details
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Reel/Frame: | 030146/0243 | |
| Pages: | 5 |
| | Recorded: | 04/03/2013 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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09/04/2012
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Application #:
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12259040
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Filing Dt:
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10/27/2008
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Publication #:
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Pub Dt:
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03/22/2012
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Title:
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WORD LINE BOOSTER FOR FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/18/2013
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Application #:
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12830241
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Filing Dt:
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07/02/2010
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Publication #:
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Pub Dt:
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06/16/2011
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Title:
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METHOD FOR DUAL ENERGY IMPLANTATION FOR ULTRA-SHALLOW JUNCTION FORMATION OF MOS DEVICES
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Patent #:
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Issue Dt:
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11/11/2014
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Application #:
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12892881
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Filing Dt:
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09/28/2010
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Publication #:
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Pub Dt:
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12/01/2011
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Title:
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SYSTEM AND METHOD FOR INTEGRATED CIRCUITS WITH CYLINDRICAL GATE STRUCTURES
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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12959279
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Filing Dt:
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12/02/2010
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Publication #:
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Pub Dt:
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12/08/2011
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Title:
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ARRAY ARCHITECTURE FOR EMBEDDED FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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08/21/2012
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Application #:
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12960357
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Filing Dt:
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12/03/2010
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Publication #:
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Pub Dt:
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05/24/2012
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Title:
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METHOD AND RESULTING STRUCTURE FOR DEEP TRENCH POLYSILICON HARD MASK REMOVAL
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Assignees
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18 ZHANG JIANG RD., PUDONG NEW AREA |
SHANGHAI, CHINA 201203 |
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18 WEN CHANG ROAD |
ECONOMIC-TECHNOLOGICAL DEVELOPMENT AREA, DAXING DISTRICT |
BEIJING, CHINA 100176 |
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Correspondence name and address
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KILPATRICK TOWNSEND & STOCKTON LLP
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TWO EMBARCADERO CENTER
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EIGHTH FLOOR
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SAN FRANCISCO, CA 94111-3834
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