Patent Assignment Details
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Reel/Frame: | 043292/0267 | |
| Pages: | 5 |
| | Recorded: | 08/15/2017 | | |
Attorney Dkt #: | PAT 81701B-2 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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03/27/2018
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Application #:
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15676676
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Filing Dt:
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08/14/2017
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Publication #:
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Pub Dt:
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11/30/2017
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Title:
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METHOD AND SYSTEM FOR FUNCTIONAL VERIFICATION AND POWER ANALYSIS OF CLOCK-GATED INTEGRATED CIRCUITS
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Assignee
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ONE ENTERPRISE |
ALISO VIEJO, CALIFORNIA 92656 |
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Correspondence name and address
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BORDEN LADNER GERVAIS LLP
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100 QUEEN STREET
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SUITE 1300
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OTTAWA, K1P 1J9 CANADA
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