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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	064783/0267			Pages:	6
		Recorded:	08/30/2023
Attorney Dkt #:	REFILE-19
Conveyance:	CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME PREVIOUSLY RECORDED AT REEL: 056602 FRAME: 0253. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME.

Total properties: 30

Patent #:	6522562	Issue Dt:	02/18/2003	Application #:	09894900	Filing Dt:	06/29/2001
Publication #:	US20020126519	Pub Dt:	09/12/2002
Title:	CONTENT ADDRESSABLE MEMORY CELL HAVING IMPROVED LAYOUT

Patent #:	6584003	Issue Dt:	06/24/2003	Application #:	10134753	Filing Dt:	04/30/2002
Title:	LOW POWER CONTENT ADDRESSABLE MEMORY ARCHITECTURE

Patent #:	6717876	Issue Dt:	04/06/2004	Application #:	10329461	Filing Dt:	12/27/2002
Publication #:	US20030137890	Pub Dt:	07/24/2003
Title:	MATCHLINE SENSING FOR CONTENT ADDRESSABLE MEMORIES

Patent #:	6873532	Issue Dt:	03/29/2005	Application #:	10351593	Filing Dt:	01/27/2003
Publication #:	US20030161173	Pub Dt:	08/28/2003
Title:	CONTENT ADDRESSABLE MEMORY CELL HAVING IMPROVED LAYOUT

Patent #:	7675925	Issue Dt:	03/09/2010	Application #:	10614558	Filing Dt:	07/07/2003
Publication #:	US20040008714	Pub Dt:	01/15/2004
Title:	METHOD AND APPARATUS FOR PROVIDING A PACKET BUFFER RANDOM ACCESS MEMORY

Patent #:	7477716	Issue Dt:	01/13/2009	Application #:	10647664	Filing Dt:	08/25/2003
Publication #:	US20040264621	Pub Dt:	12/30/2004
Title:	START UP CIRCUIT FOR DELAY LOCKED LOOP

Patent #:	7123056	Issue Dt:	10/17/2006	Application #:	10730002	Filing Dt:	12/09/2003
Publication #:	US20040164769	Pub Dt:	08/26/2004
Title:	CLOCK LOGIC DOMINO CIRCUITS FOR HIGH-SPEED AND ENERGY EFFICIENT MICROPROCESSOR PIPELINES

Patent #:	7051306	Issue Dt:	05/23/2006	Application #:	10840893	Filing Dt:	05/07/2004
Publication #:	US20040268278	Pub Dt:	12/30/2004
Title:	MANAGING POWER ON INTEGRATED CIRCUITS USING POWER ISLANDS

Patent #:	7652922	Issue Dt:	01/26/2010	Application #:	11324023	Filing Dt:	12/30/2005
Publication #:	US20070076479	Pub Dt:	04/05/2007
Title:	MULTIPLE INDEPENDENT SERIAL LINK MEMORY

Patent #:	7415680	Issue Dt:	08/19/2008	Application #:	11336097	Filing Dt:	01/20/2006
Publication #:	US20060123365	Pub Dt:	06/08/2006
Title:	POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Patent #:	9240227	Issue Dt:	01/19/2016	Application #:	11594564	Filing Dt:	11/08/2006
Publication #:	US20070109833	Pub Dt:	05/17/2007
Title:	DAISY CHAIN CASCADING DEVICES

Patent #:	7511980	Issue Dt:	03/31/2009	Application #:	11747428	Filing Dt:	05/11/2007
Publication #:	US20070206397	Pub Dt:	09/06/2007
Title:	LOW POWER MATCH-LINE SENSING CIRCUIT

Patent #:	7945885	Issue Dt:	05/17/2011	Application #:	12176645	Filing Dt:	07/21/2008
Publication #:	US20080276105	Pub Dt:	11/06/2008
Title:	POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Patent #:	7719892	Issue Dt:	05/18/2010	Application #:	12179835	Filing Dt:	07/25/2008
Publication #:	US20080279003	Pub Dt:	11/13/2008
Title:	FLASH MEMORY DEVICE WITH DATA OUTPUT CONTROL

Patent #:	7656988	Issue Dt:	02/02/2010	Application #:	12315289	Filing Dt:	12/02/2008
Publication #:	US20090086876	Pub Dt:	04/02/2009
Title:	START UP CIRCUIT FOR DELAY LOCKED LOOP

Patent #:	7996811	Issue Dt:	08/09/2011	Application #:	12332529	Filing Dt:	12/11/2008
Publication #:	US20090152948	Pub Dt:	06/18/2009
Title:	POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Patent #:	8218707	Issue Dt:	07/10/2012	Application #:	12639531	Filing Dt:	12/16/2009
Publication #:	US20100109722	Pub Dt:	05/06/2010
Title:	INITIALIZATION CIRCUIT FOR DELAY LOCKED LOOP

Patent #:	8000144	Issue Dt:	08/16/2011	Application #:	12732745	Filing Dt:	03/26/2010
Publication #:	US20100182838	Pub Dt:	07/22/2010
Title:	METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE

Patent #:	8782590	Issue Dt:	07/15/2014	Application #:	13164362	Filing Dt:	06/20/2011
Publication #:	US20120043812	Pub Dt:	02/23/2012
Title:	POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Patent #:	8743610	Issue Dt:	06/03/2014	Application #:	13171667	Filing Dt:	06/29/2011
Publication #:	US20110255339	Pub Dt:	10/20/2011
Title:	METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE

Patent #:	8762923	Issue Dt:	06/24/2014	Application #:	13473129	Filing Dt:	05/16/2012
Publication #:	US20120256485	Pub Dt:	10/11/2012
Title:	POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Patent #:	8503598	Issue Dt:	08/06/2013	Application #:	13532980	Filing Dt:	06/26/2012
Publication #:	US20120306548	Pub Dt:	12/06/2012
Title:	INITIALIZATION CIRCUIT FOR DELAY LOCKED LOOP

Patent #:	9230654	Issue Dt:	01/05/2016	Application #:	13790361	Filing Dt:	03/08/2013
Publication #:	US20130188422	Pub Dt:	07/25/2013
Title:	METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE

Patent #:	9166412	Issue Dt:	10/20/2015	Application #:	14324297	Filing Dt:	07/07/2014
Publication #:	US20140333134	Pub Dt:	11/13/2014
Title:	POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Patent #:	9660616	Issue Dt:	05/23/2017	Application #:	14865905	Filing Dt:	09/25/2015
Publication #:	US20160087608	Pub Dt:	03/24/2016
Title:	POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Patent #:	9490014	Issue Dt:	11/08/2016	Application #:	14964958	Filing Dt:	12/10/2015
Publication #:	US20160196878	Pub Dt:	07/07/2016
Title:	METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE

Patent #:	9836227	Issue Dt:	12/05/2017	Application #:	15273122	Filing Dt:	09/22/2016
Publication #:	US20170109059	Pub Dt:	04/20/2017
Title:	METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE

Patent #:	10243542	Issue Dt:	03/26/2019	Application #:	15490557	Filing Dt:	04/18/2017
Publication #:	US20170288649	Pub Dt:	10/05/2017
Title:	POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Patent #:	10223003	Issue Dt:	03/05/2019	Application #:	15807720	Filing Dt:	11/09/2017
Publication #:	US20180129427	Pub Dt:	05/10/2018
Title:	METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE

Patent #:	10749506	Issue Dt:	08/18/2020	Application #:	16226917	Filing Dt:	12/20/2018
Publication #:	US20190173453	Pub Dt:	06/06/2019
Title:	POWER MANAGERS FOR AN INTEGRATED CIRCUIT

Assignor

CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Exec Dt:

04/01/2021

Assignee

MOSAID TECHNOLOGIES INCORPORATED

515 LEGGET DRIVE

SUITE 100

OTTAWA, CANADA K2K 3G4

Correspondence name and address
	CONVERSANT IP MANAGEMENT CORP.
	5830 GRANITE PARKWAY #100-247
	PLANO, TX 75024

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