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Reel/Frame:049233/0278   Pages: 5
Recorded: 05/20/2019
Attorney Dkt #:SOCTRONICS-INVECAS_ASSIGN
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 9
1
Patent #:
Issue Dt:
03/11/2014
Application #:
13667290
Filing Dt:
11/02/2012
Publication #:
Pub Dt:
03/07/2013
Title:
Voltage Mode Driver Using Pre-emphasis and De-emphasis Signals
2
Patent #:
Issue Dt:
02/04/2014
Application #:
13669137
Filing Dt:
11/05/2012
Title:
Parallel-to-Serial Converter
3
Patent #:
Issue Dt:
03/15/2016
Application #:
13851767
Filing Dt:
03/27/2013
Publication #:
Pub Dt:
10/02/2014
Title:
Serial-to-Parallel Converter Using Serially-Connected Stages
4
Patent #:
Issue Dt:
05/10/2016
Application #:
13922193
Filing Dt:
06/19/2013
Publication #:
Pub Dt:
10/23/2014
Title:
METHODS AND SYSTEMS FOR DETERMINING WHETHER A RECEIVER IS PRESENT ON A PCI-EXPRESS BUS
5
Patent #:
Issue Dt:
02/10/2015
Application #:
14065754
Filing Dt:
10/29/2013
Publication #:
Pub Dt:
10/23/2014
Title:
Methods and Systems for Calibration of a Delay Locked Loop
6
Patent #:
Issue Dt:
02/07/2017
Application #:
14066583
Filing Dt:
10/29/2013
Publication #:
Pub Dt:
10/23/2014
Title:
Methods and Systems for Clocking a Physical Layer Interface
7
Patent #:
Issue Dt:
10/11/2016
Application #:
14170064
Filing Dt:
01/31/2014
Publication #:
Pub Dt:
10/23/2014
Title:
Methods and Systems for Distributing Clock and Reset Signals Across An Address Macro
8
Patent #:
Issue Dt:
05/24/2016
Application #:
14171646
Filing Dt:
02/03/2014
Publication #:
Pub Dt:
08/06/2015
Title:
Memory Interface
9
Patent #:
Issue Dt:
04/17/2018
Application #:
15145735
Filing Dt:
05/03/2016
Publication #:
Pub Dt:
08/25/2016
Title:
METHODS AND SYSTEMS FOR CLOCKING A PHYSICAL LAYER INTERFACE
Assignor
1
Exec Dt:
05/20/2019
Assignee
1
3385 SCOTT BOULEVARD
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
DANIEL HOPEN
425 N WHISMAN RD, SUITE 800
MOUNTAIN VIEW, CA 94043

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