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Reel/Frame:	064180/0278			Pages:	8
		Recorded:	06/30/2023
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 56

Patent #:	7465676	Issue Dt:	12/16/2008	Application #:	11409658	Filing Dt:	04/24/2006
Publication #:	US20070249159	Pub Dt:	10/25/2007
Title:	METHOD FOR FORMING DIELECTRIC FILM TO IMPROVE ADHESION OF LOW-K FILM

Patent #:	7772701	Issue Dt:	08/10/2010	Application #:	11422769	Filing Dt:	06/07/2006
Publication #:	US20070284747	Pub Dt:	12/13/2007
Title:	INTEGRATED CIRCUIT HAVING IMPROVED INTERCONNECT STRUCTURE

Patent #:	7663185	Issue Dt:	02/16/2010	Application #:	11441724	Filing Dt:	05/27/2006
Publication #:	US20070272954	Pub Dt:	11/29/2007
Title:	FIN-FET DEVICE STRUCTURE FORMED EMPLOYING BULK SEMICONDUCTOR SUBSTRATE

Patent #:	8432040	Issue Dt:	04/30/2013	Application #:	11444629	Filing Dt:	06/01/2006
Publication #:	US20070278681	Pub Dt:	12/06/2007
Title:	INTERCONNECTION STRUCTURE DESIGN FOR LOW RC DELAY AND LEAKAGE

Patent #:	7791170	Issue Dt:	09/07/2010	Application #:	11456291	Filing Dt:	07/10/2006
Publication #:	US20080014673	Pub Dt:	01/17/2008
Title:	METHOD OF MAKING A DEEP JUNCTION FOR ELECTRICAL CROSSTALK REDUCTION OF AN IMAGE SENSOR

Patent #:	7465634	Issue Dt:	12/16/2008	Application #:	11583500	Filing Dt:	10/18/2006
Publication #:	US20080096336	Pub Dt:	04/24/2008
Title:	METHOD OF FORMING INTEGRATED CIRCUIT DEVICES HAVING N-MOSFET AND P-MOSFET TRANSISTORS WITH ELEVATED AND SILICIDED SOURCE/DRAIN STRUCTURES

Patent #:	7485940	Issue Dt:	02/03/2009	Application #:	11626757	Filing Dt:	01/24/2007
Publication #:	US20080173963	Pub Dt:	07/24/2008
Title:	GUARD RING STRUCTURE FOR IMPROVING CROSSTALK OF BACKSIDE ILLUMINATED IMAGE SENSOR

Patent #:	7812459	Issue Dt:	10/12/2010	Application #:	11641324	Filing Dt:	12/19/2006
Publication #:	US20080142990	Pub Dt:	06/19/2008
Title:	THREE-DIMENSIONAL INTEGRATED CIRCUITS WITH PROTECTION LAYERS

Patent #:	7514797	Issue Dt:	04/07/2009	Application #:	11756347	Filing Dt:	05/31/2007
Publication #:	US20080296763	Pub Dt:	12/04/2008
Title:	MULTI-DIE WAFER LEVEL PACKAGING

Patent #:	7576435	Issue Dt:	08/18/2009	Application #:	11796297	Filing Dt:	04/27/2007
Publication #:	US20080265399	Pub Dt:	10/30/2008
Title:	LOW-COST AND ULTRA-FINE INTEGRATED CIRCUIT PACKAGING TECHNIQUE

Patent #:	7820543	Issue Dt:	10/26/2010	Application #:	11807522	Filing Dt:	05/29/2007
Publication #:	US20080296764	Pub Dt:	12/04/2008
Title:	ENHANCED COPPER POSTS FOR WAFER LEVEL CHIP SCALE PACKAGING

Patent #:	8174073	Issue Dt:	05/08/2012	Application #:	11807652	Filing Dt:	05/30/2007
Publication #:	US20080296702	Pub Dt:	12/04/2008
Title:	INTEGRATED CIRCUIT STRUCTURES WITH MULTIPLE FINFETS

Patent #:	7910994	Issue Dt:	03/22/2011	Application #:	11872546	Filing Dt:	10/15/2007
Publication #:	US20090096002	Pub Dt:	04/16/2009
Title:	SYSTEM AND METHOD FOR SOURCE/DRAIN CONTACT PROCESSING

Patent #:	8035165	Issue Dt:	10/11/2011	Application #:	12341891	Filing Dt:	12/22/2008
Publication #:	US20100052075	Pub Dt:	03/04/2010
Title:	INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS

Patent #:	7785927	Issue Dt:	08/31/2010	Application #:	12392918	Filing Dt:	02/25/2009
Publication #:	US20090155957	Pub Dt:	06/18/2009
Title:	MULTI-DIE WAFER LEVEL PACKAGING

Patent #:	9159808	Issue Dt:	10/13/2015	Application #:	12617463	Filing Dt:	11/12/2009
Publication #:	US20100190345	Pub Dt:	07/29/2010
Title:	SELECTIVE ETCH-BACK PROCESS FOR SEMICONDUCTOR DEVICES

Patent #:	8436473	Issue Dt:	05/07/2013	Application #:	12718616	Filing Dt:	03/05/2010
Publication #:	US20110215477	Pub Dt:	09/08/2011
Title:	INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES, AND FABRICATION METHODS THEREOF

Patent #:	8716862	Issue Dt:	05/06/2014	Application #:	12760732	Filing Dt:	04/15/2010
Publication #:	US20100283152	Pub Dt:	11/11/2010
Title:	INTEGRATED CIRCUIT INCLUDING A GATE AND A METALLIC CONNECTING LINE

Patent #:	8399931	Issue Dt:	03/19/2013	Application #:	12827690	Filing Dt:	06/30/2010
Publication #:	US20120001197	Pub Dt:	01/05/2012
Title:	LAYOUT FOR MULTIPLE-FIN SRAM CELL

Patent #:	8791549	Issue Dt:	07/29/2014	Application #:	12832019	Filing Dt:	07/07/2010
Publication #:	US20110068466	Pub Dt:	03/24/2011
Title:	WAFER BACKSIDE INTERCONNECT STRUCTURE CONNECTED TO TSVS

Patent #:	8093120	Issue Dt:	01/10/2012	Application #:	12839994	Filing Dt:	07/20/2010
Publication #:	US20100285658	Pub Dt:	11/11/2010
Title:	INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS

Patent #:	8373238	Issue Dt:	02/12/2013	Application #:	12843595	Filing Dt:	07/26/2010
Publication #:	US20110133292	Pub Dt:	06/09/2011
Title:	FINFETS WITH MULTIPLE FIN HEIGHTS

Patent #:	8053277	Issue Dt:	11/08/2011	Application #:	12878112	Filing Dt:	09/09/2010
Publication #:	US20100330743	Pub Dt:	12/30/2010
Title:	THREE-DIMENSIONAL INTEGRATED CIRCUITS WITH PROTECTION LAYERS

Patent #:	7932601	Issue Dt:	04/26/2011	Application #:	12899168	Filing Dt:	10/06/2010
Publication #:	US20110057313	Pub Dt:	03/10/2011
Title:	ENHANCED COPPER POSTS FOR WAFER LEVEL CHIP SCALE PACKAGING

Patent #:	8338305	Issue Dt:	12/25/2012	Application #:	12907272	Filing Dt:	10/19/2010
Publication #:	US20120091511	Pub Dt:	04/19/2012
Title:	MULTI-FIN DEVICE BY SELF-ALIGNED CASTLE FIN FORMATION

Patent #:	8143114	Issue Dt:	03/27/2012	Application #:	13027436	Filing Dt:	02/15/2011
Publication #:	US20110171805	Pub Dt:	07/14/2011
Title:	SYSTEM AND METHOD FOR SOURCE/DRAIN CONTACT PROCESSING

Patent #:	8148826	Issue Dt:	04/03/2012	Application #:	13273845	Filing Dt:	10/14/2011
Publication #:	US20120032348	Pub Dt:	02/09/2012
Title:	THREE-DIMENSIONAL INTEGRATED CIRCUITS WITH PROTECTION LAYERS

Patent #:	8394692	Issue Dt:	03/12/2013	Application #:	13286276	Filing Dt:	11/01/2011
Publication #:	US20120045889	Pub Dt:	02/23/2012
Title:	INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS

Patent #:	11038056	Issue Dt:	06/15/2021	Application #:	13371169	Filing Dt:	02/10/2012
Publication #:	US20120211807	Pub Dt:	08/23/2012
Title:	System and Method for Source/Drain Contact Processing

Patent #:	8405225	Issue Dt:	03/26/2013	Application #:	13437533	Filing Dt:	04/02/2012
Publication #:	US20120187576	Pub Dt:	07/26/2012
Title:	Three-Dimensional Integrated Circuits with Protection Layers

Patent #:	9165968	Issue Dt:	10/20/2015	Application #:	13616850	Filing Dt:	09/14/2012
Publication #:	US20140077057	Pub Dt:	03/20/2014
Title:	3D-STACKED BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MAKING THE SAME

Patent #:	8878308	Issue Dt:	11/04/2014	Application #:	13724709	Filing Dt:	12/21/2012
Publication #:	US20130113023	Pub Dt:	05/09/2013
Title:	MULTI-FIN DEVICE BY SELF-ALIGNED CASTLE FIN FORMATION

Patent #:	8673709	Issue Dt:	03/18/2014	Application #:	13764549	Filing Dt:	02/11/2013
Publication #:	US20130149826	Pub Dt:	06/13/2013
Title:	FINFETS WITH MULTIPLE FIN HEIGHTS

Patent #:	8669153	Issue Dt:	03/11/2014	Application #:	13794621	Filing Dt:	03/11/2013
Publication #:	US20130196496	Pub Dt:	08/01/2013
Title:	INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS

Patent #:	8653630	Issue Dt:	02/18/2014	Application #:	13797190	Filing Dt:	03/12/2013
Publication #:	US20130200395	Pub Dt:	08/08/2013
Title:	LAYOUT FOR MULTIPLE-FIN SRAM CELL

Patent #:	8847405	Issue Dt:	09/30/2014	Application #:	13858639	Filing Dt:	04/08/2013
Publication #:	US20130221541	Pub Dt:	08/29/2013
Title:	INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES, AND FABRICATION METHODS THEREOF

Patent #:	8748993	Issue Dt:	06/10/2014	Application #:	14046188	Filing Dt:	10/04/2013
Publication #:	US20140035043	Pub Dt:	02/06/2014
Title:	FINFETS WITH MULTIPLE FIN HEIGHTS

Patent #:	9059061	Issue Dt:	06/16/2015	Application #:	14143848	Filing Dt:	12/30/2013
Publication #:	US20140264508	Pub Dt:	09/18/2014
Title:	Structure and Method for 3D Image Sensor

Patent #:	9153484	Issue Dt:	10/06/2015	Application #:	14245192	Filing Dt:	04/04/2014
Publication #:	US20140220769	Pub Dt:	08/07/2014
Title:	METHODS OF FORMING INTEGRATED CIRCUITS

Patent #:	9087725	Issue Dt:	07/21/2015	Application #:	14277160	Filing Dt:	05/14/2014
Publication #:	US20140284723	Pub Dt:	09/25/2014
Title:	FINFETS WITH DIFFERENT FIN HEIGHT AND EPI HEIGHT SETTING

Patent #:	9881993	Issue Dt:	01/30/2018	Application #:	14317069	Filing Dt:	06/27/2014
Publication #:	US20150380313	Pub Dt:	12/31/2015
Title:	METHOD OF FORMING SEMICONDUCTOR STRUCTURE WITH HORIZONTAL GATE ALL AROUND STRUCTURE

Patent #:	9716074	Issue Dt:	07/25/2017	Application #:	14323617	Filing Dt:	07/03/2014
Publication #:	US20140312494	Pub Dt:	10/23/2014
Title:	WAFER BACKSIDE INTERCONNECT STRUCTURE CONNECTED TO TSVS

Patent #:	9449875	Issue Dt:	09/20/2016	Application #:	14323677	Filing Dt:	07/03/2014
Publication #:	US20140322909	Pub Dt:	10/30/2014
Title:	WAFER BACKSIDE INTERCONNECT STRUCTURE CONNECTED TO TSVS

Patent #:	9147602	Issue Dt:	09/29/2015	Application #:	14493992	Filing Dt:	09/23/2014
Publication #:	US20150044865	Pub Dt:	02/12/2015
Title:	METHODS OF MAKING INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES

Patent #:	10115788	Issue Dt:	10/30/2018	Application #:	14512963	Filing Dt:	10/13/2014
Publication #:	US20160104765	Pub Dt:	04/14/2016
Title:	SEMICONDUCTOR DEVICES WITH HORIZONTAL GATE ALL AROUND STRUCTURE AND METHODS OF FORMING THE SAME

Patent #:	9312186	Issue Dt:	04/12/2016	Application #:	14532074	Filing Dt:	11/04/2014
Publication #:	US20160126143	Pub Dt:	05/05/2016
Title:	METHOD OF FORMING HORIZONTAL GATE ALL AROUND STRUCTURE

Patent #:	9525003	Issue Dt:	12/20/2016	Application #:	14739514	Filing Dt:	06/15/2015
Publication #:	US20150279893	Pub Dt:	10/01/2015
Title:	Structure and Method for 3D Image Sensor

Patent #:	9257344	Issue Dt:	02/09/2016	Application #:	14752316	Filing Dt:	06/26/2015
Publication #:	US20150303116	Pub Dt:	10/22/2015
Title:	FinFETs with Different Fin Height and EPI Height Setting

Patent #:	9721829	Issue Dt:	08/01/2017	Application #:	15003909	Filing Dt:	01/22/2016
Publication #:	US20160141205	Pub Dt:	05/19/2016
Title:	FinFETs with Different Fin Height and EPI Height Setting

Patent #:	RE47409	Issue Dt:	05/28/2019	Application #:	15041843	Filing Dt:	02/11/2016
Title:	LAYOUT FOR MULTIPLE-FIN SRAM CELL

Patent #:	9786757	Issue Dt:	10/10/2017	Application #:	15063601	Filing Dt:	03/08/2016
Publication #:	US20160190272	Pub Dt:	06/30/2016
Title:	METHOD OF FORMING HORIZONTAL GATE ALL AROUND STRUCTURE

Patent #:	9978708	Issue Dt:	05/22/2018	Application #:	15269613	Filing Dt:	09/19/2016
Publication #:	US20170005069	Pub Dt:	01/05/2017
Title:	Wafer Backside Interconnect Structure Connected to TSVs

Patent #:	9812487	Issue Dt:	11/07/2017	Application #:	15383924	Filing Dt:	12/19/2016
Publication #:	US20170098679	Pub Dt:	04/06/2017
Title:	Structure and Method for 3D Image Sensor

Patent #:	10535697	Issue Dt:	01/14/2020	Application #:	15803913	Filing Dt:	11/06/2017
Publication #:	US20180061880	Pub Dt:	03/01/2018
Title:	Structure and Method for 3D Image Sensor

Patent #:	RE49203	Issue Dt:	09/06/2022	Application #:	16422627	Filing Dt:	05/24/2019
Title:	Layout for Multiple-Fin SRAM Cell

Patent #:	11011567	Issue Dt:	05/18/2021	Application #:	16678425	Filing Dt:	11/08/2019
Publication #:	US20200075659	Pub Dt:	03/05/2020
Title:	Structure and Method for 3D Image Sensor

Assignor

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Exec Dt:

06/20/2023

Assignee

ADVANCED MANUFACTURING INNOVATIONS INC.

251 LITTLE FALLS DRIVE

WILMINGTON, DELAWARE 19808

Correspondence name and address
	MICHAEL MCCARTNEY
	1891 ROBERTSON RD. SUITE 100
	OTTAWA, K2H5B7 CANADA

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