Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 018093/0282 | |
| Pages: | 10 |
| | Recorded: | 07/11/2006 | | |
Attorney Dkt #: | 09230.0999 |
Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
8
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11318477
|
Filing Dt:
|
12/28/2005
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
VERTICAL-TYPE CAPACITOR STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11318587
|
Filing Dt:
|
12/28/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
Method for rounding top corners of isolation trench in semiconductor device
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
11318589
|
Filing Dt:
|
12/28/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
METALLIZATION METHOD OF SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11319531
|
Filing Dt:
|
12/29/2005
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
Title:
|
METHOD OF FORMING DOUBLE GATE DIELECTRIC LAYERS AND SEMICONDUCTOR DEVICE HAVING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11320303
|
Filing Dt:
|
12/29/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING SILICIDE-BLOCKING LAYER AND FABRICATION METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
11320304
|
Filing Dt:
|
12/29/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
METALLIZATION METHOD OF SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
11320605
|
Filing Dt:
|
12/30/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
METHOD FOR FORMING SPLIT GATE FLASH NONVOLATILE MEMORY DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11320979
|
Filing Dt:
|
12/30/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
Method for forming resistors in semiconductor integrated circuit devices
|
|
Assignee
|
|
|
891-10 DAECHI-DONG, KANGNAM-KU |
SEOUL, KOREA, REPUBLIC OF 135-523 |
|
Correspondence name and address
|
|
FINNEGAN, HENDERSON, FARABOW,
|
|
GARRETT & DUNNER, LLP
|
|
901 NEW YORK AVENUE, NW
|
|
WASHINGTON, DC 20001-4413
|
Search Results as of:
06/19/2024 05:55 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|