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Patent Assignment Details

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Reel/Frame:	046589/0282			Pages:	3
		Recorded:	08/08/2018
Attorney Dkt #:	075803.0000LASTPART2
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 29

Patent #:	7181600	Issue Dt:	02/20/2007	Application #:	09921377	Filing Dt:	08/02/2001
Title:	READ-ONLY ACCESS TO CPO REGISTERS

Patent #:	7185183	Issue Dt:	02/27/2007	Application #:	09921400	Filing Dt:	08/02/2001
Title:	ATOMIC UPDATE OF CPO STATE

Patent #:	7552261	Issue Dt:	06/23/2009	Application #:	09977089	Filing Dt:	10/12/2001
Publication #:	US20030074508	Pub Dt:	04/17/2003
Title:	CONFIGURABLE PRIORITIZATION OF CORE GENERATED INTERRUPTS

Patent #:	7000095	Issue Dt:	02/14/2006	Application #:	10238993	Filing Dt:	09/06/2002
Publication #:	US20040049660	Pub Dt:	03/11/2004
Title:	METHOD AND APPARATUS FOR CLEARING HAZARDS USING JUMP INSTRUCTIONS

Patent #:	7376954	Issue Dt:	05/20/2008	Application #:	10684350	Filing Dt:	10/10/2003
Publication #:	US20050050395	Pub Dt:	03/03/2005
Title:	MECHANISMS FOR ASSURING QUALITY OF SERVICE FOR PROGRAMS EXECUTING ON A MULTITHREADED PROCESSOR

Patent #:	7644237	Issue Dt:	01/05/2010	Application #:	10783960	Filing Dt:	02/20/2004
Title:	METHOD AND APPARATUS FOR GLOBAL ORDERING TO INSURE LATENCY INDEPENDENT COHERENCE

Patent #:	7711931	Issue Dt:	05/04/2010	Application #:	10954988	Filing Dt:	09/30/2004
Publication #:	US20070186028	Pub Dt:	08/09/2007
Title:	SYNCHRONIZED STORAGE PROVIDING MULTIPLE SYNCHRONIZATION SEMANTICS

Patent #:	7853777	Issue Dt:	12/14/2010	Application #:	11051978	Filing Dt:	02/04/2005
Publication #:	US20060179274	Pub Dt:	08/10/2006
Title:	INSTRUCTION/SKID BUFFERS IN A MULTITHREADING MICROPROCESSOR THAT STORE DISPATCHED INSTRUCTIONS TO AVOID RE-FETCHING FLUSHED INSTRUCTIONS

Patent #:	7613904	Issue Dt:	11/03/2009	Application #:	11051997	Filing Dt:	02/04/2005
Publication #:	US20060179279	Pub Dt:	08/10/2006
Title:	INTERFACING EXTERNAL THREAD PRIORITIZING POLICY ENFORCING LOGIC WITH CUSTOMER MODIFIABLE REGISTER TO PROCESSOR INTERNAL SCHEDULER

Patent #:	7558939	Issue Dt:	07/07/2009	Application #:	11075041	Filing Dt:	03/08/2005
Publication #:	US20060206686	Pub Dt:	09/14/2006
Title:	THREE-TIERED TRANSLATION LOOKASIDE BUFFER HIERARCHY IN A MULTITHREADING MICROPROCESSOR

Patent #:	8171262	Issue Dt:	05/01/2012	Application #:	11284069	Filing Dt:	11/21/2005
Publication #:	US20060101255	Pub Dt:	05/11/2006
Title:	METHOD AND APPARATUS FOR CLEARING HAZARDS USING JUMP INSTRUCTIONS

Patent #:	7600100	Issue Dt:	10/06/2009	Application #:	11567290	Filing Dt:	12/06/2006
Publication #:	US20070234020	Pub Dt:	10/04/2007
Title:	INSTRUCTION ENCODING FOR SYSTEM REGISTER BIT SET AND CLEAR

Patent #:	7774549	Issue Dt:	08/10/2010	Application #:	11681610	Filing Dt:	03/02/2007
Publication #:	US20080091880	Pub Dt:	04/17/2008
Title:	HORIZONTALLY-SHARED CACHE VICTIMS IN MULTIPLE CORE PROCESSORS

Patent #:	8037253	Issue Dt:	10/11/2011	Application #:	12557421	Filing Dt:	09/10/2009
Publication #:	US20100005247	Pub Dt:	01/07/2010
Title:	METHOD AND APPARATUS FOR GLOBAL ORDERING TO INSURE LATENCY INDEPENDENT COHERENCE

Patent #:	8190865	Issue Dt:	05/29/2012	Application #:	12576942	Filing Dt:	10/09/2009
Publication #:	US20100031005	Pub Dt:	02/04/2010
Title:	INSTRUCTION ENCODING FOR SYSTEM REGISTER BIT SET AND CLEAR

Patent #:	8151268	Issue Dt:	04/03/2012	Application #:	12684564	Filing Dt:	01/08/2010
Publication #:	US20100115244	Pub Dt:	05/06/2010
Title:	MULTITHREADING MICROPROCESSOR WITH OPTIMIZED THREAD SCHEDULER FOR INCREASING PIPELINE UTILIZATION EFFICIENCY

Patent #:	8239620	Issue Dt:	08/07/2012	Application #:	12891503	Filing Dt:	09/27/2010
Publication #:	US20120079164	Pub Dt:	03/29/2012
Title:	MICROPROCESSOR WITH DUAL-LEVEL ADDRESS TRANSLATION

Patent #:	8789042	Issue Dt:	07/22/2014	Application #:	12891530	Filing Dt:	09/27/2010
Publication #:	US20120079479	Pub Dt:	03/29/2012
Title:	MICROPROCESSOR SYSTEM FOR VIRTUAL MACHINE EXECUTION

Patent #:	9086906	Issue Dt:	07/21/2015	Application #:	13436654	Filing Dt:	03/30/2012
Publication #:	US20130263124	Pub Dt:	10/03/2013
Title:	Apparatus and Method for Guest and Root Register Sharing in a Virtual Machine

Patent #:	9128700	Issue Dt:	09/08/2015	Application #:	13563025	Filing Dt:	07/31/2012
Publication #:	US20130179665	Pub Dt:	07/11/2013
Title:	RESTORING A REGISTER RENAMING MAP

Patent #:	9235510	Issue Dt:	01/12/2016	Application #:	13683875	Filing Dt:	11/21/2012
Publication #:	US20130132702	Pub Dt:	05/23/2013
Title:	Processor with Kernel Mode Access to User Space Virtual Addresses

Patent #:	NONE	Issue Dt:		Application #:	13774140	Filing Dt:	02/22/2013
Publication #:	US20140244977	Pub Dt:	08/28/2014
Title:	Deferred Saving of Registers in a Shared Register Pool for a Multithreaded Microprocessor

Patent #:	9189412	Issue Dt:	11/17/2015	Application #:	13789443	Filing Dt:	03/07/2013
Publication #:	US20140258624	Pub Dt:	09/11/2014
Title:	Apparatus and Method for Operating a Processor with an Operation Cache

Patent #:	9436470	Issue Dt:	09/06/2016	Application #:	14816651	Filing Dt:	08/03/2015
Publication #:	US20150339123	Pub Dt:	11/26/2015
Title:	Restoring a Register Renaming Map

Patent #:	10185665	Issue Dt:	01/22/2019	Application #:	15824613	Filing Dt:	11/28/2017
Publication #:	US20180089102	Pub Dt:	03/29/2018
Title:	Translation Lookaside Buffer

Patent #:	10678695	Issue Dt:	06/09/2020	Application #:	15833555	Filing Dt:	12/06/2017
Publication #:	US20180095885	Pub Dt:	04/05/2018
Title:	Migration of Data to Register File Cache

Patent #:	10379861	Issue Dt:	08/13/2019	Application #:	15874724	Filing Dt:	01/18/2018
Publication #:	US20180143835	Pub Dt:	05/24/2018
Title:	Decoding Instructions That Are Modified By One Or More Other Instructions

Assignor

Exec Dt:

11/08/2017

Assignee

IMAGINATION HOUSE

HOME PARK ESTATE

KINGS LANGLEY, UNITED KINGDOM WD4 8LZ

Correspondence name and address
	VORYS, SATER, SEYMOUR AND PEASE LLP
	1909 K STREET, N.W.
	9TH FLOOR
	WASHINGTON, DC 20006

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