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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:013795/0288   Pages: 3
Recorded: 03/03/2003
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 7
1
Patent #:
NONE
Issue Dt:
Application #:
10252898
Filing Dt:
09/23/2002
Publication #:
Pub Dt:
01/30/2003
Title:
Semiconductor device and process for production thereof
2
Patent #:
Issue Dt:
09/21/2004
Application #:
10255373
Filing Dt:
09/26/2002
Publication #:
Pub Dt:
03/27/2003
Title:
SOLDER BALL AND INTERCONNECTION STRUCTURE USING THE SAME
3
Patent #:
Issue Dt:
12/21/2004
Application #:
10257193
Filing Dt:
10/09/2002
Publication #:
Pub Dt:
04/03/2003
Title:
SEMICONDUCTOR STORAGE DEVICE
4
Patent #:
Issue Dt:
10/26/2004
Application #:
10258334
Filing Dt:
10/21/2002
Publication #:
Pub Dt:
06/19/2003
Title:
SEMICONDUCTOR STORAGE DEVICE
5
Patent #:
NONE
Issue Dt:
Application #:
10274555
Filing Dt:
10/21/2002
Publication #:
Pub Dt:
02/20/2003
Title:
METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH LOWER LAYER WIRING AND VIA HOLE
6
Patent #:
Issue Dt:
07/27/2004
Application #:
10303275
Filing Dt:
11/25/2002
Publication #:
Pub Dt:
05/29/2003
Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
7
Patent #:
Issue Dt:
03/30/2004
Application #:
10333935
Filing Dt:
01/23/2003
Publication #:
Pub Dt:
08/14/2003
Title:
SEMICONDUCTOR MEMORY AND CONTROL METHOD
Assignor
1
Exec Dt:
11/01/2002
Assignee
1
1753 SHIMONUMABE, NAKAHARA-KU
KAWASAKI, KANAGAWA 211-8668, JAPAN
Correspondence name and address
CHOATE, HALL & STEWART
DONALD W. MUIRHEAD
53 STATE STREET, EXCHANGE PLACE
PATENT GROUP
BOSTON, MA 02109

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