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Total properties:
10
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Patent #:
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Issue Dt:
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06/27/1995
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Application #:
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08159551
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Filing Dt:
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12/01/1993
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Title:
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METHOD OF MAKING A CONTACT OF A SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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|
Issue Dt:
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04/23/1996
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Application #:
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08248754
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Filing Dt:
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05/25/1994
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Title:
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PROCESS FOR ANISOTROPICALLY ETCHING SEMICONDUCTOR MATERIAL
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|
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Patent #:
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|
Issue Dt:
|
06/25/1996
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Application #:
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08421793
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Filing Dt:
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04/14/1995
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Title:
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A SEMICONDUCTOR CONTACT THAT PARTIALLY OVERLAPS A CONDUCTIVE LINE PATTERN AND A METHOD OF MANUFACTURING SAME
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|
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Patent #:
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Issue Dt:
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07/14/1998
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Application #:
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08669746
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Filing Dt:
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06/26/1996
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Title:
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SENSE AMPLIFIER WITH LOW POWER IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
06/02/1998
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Application #:
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08708742
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Filing Dt:
|
09/05/1996
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Title:
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METHOD FOR MANUFACTURING MOSFET
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Patent #:
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|
Issue Dt:
|
04/29/2003
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Application #:
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09742816
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Filing Dt:
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12/19/2000
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Publication #:
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Pub Dt:
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09/13/2001
| | | | |
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Title:
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DELAY LOCKED LOOP FOR USE IN SEMICONDUCTOR MEMORY DEVICE
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|
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Patent #:
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Issue Dt:
|
01/28/2003
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Application #:
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09883188
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Filing Dt:
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06/19/2001
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Publication #:
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|
Pub Dt:
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01/24/2002
| | | | |
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Title:
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METHOD FOR MAKING HIGH K DIELECTRIC GATE FOR SEMICONDUCTOR DEVICE
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|
|
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Patent #:
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Issue Dt:
|
01/02/2007
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Application #:
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10036156
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Filing Dt:
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12/26/2001
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Publication #:
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Pub Dt:
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07/04/2002
| | | | |
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Title:
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METHOD OF FORMING A METAL GATE IN A SEMICONDUCTOR DEVICE USING ATOMIC LAYER DEPOSITION PROCESS
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|
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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10298564
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Filing Dt:
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11/19/2002
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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GATE STRUCTURE WITH HIGH K DIELECTRIC
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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10879650
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Filing Dt:
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06/28/2004
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Publication #:
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Pub Dt:
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08/18/2005
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Title:
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ON DIE TERMINATION MODE TRANSFER CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE AND ITS METHOD
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|
