Total properties:
58
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Patent #:
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Issue Dt:
|
08/02/1983
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Application #:
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06355445
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Filing Dt:
|
04/30/1982
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Title:
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ION ETCHING PROCESS WITH MINIMIZED REDEPOSITION
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Patent #:
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Issue Dt:
|
10/23/1984
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Application #:
|
06397050
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Filing Dt:
|
07/12/1982
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Title:
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PROCESS FOR AND STRUCTURE OF HIGH DENSITY VLSI CIRCUITS, HAVING SELF- ALIGNED GATES AND CONTACTS FOR FET DEVICES AND CONDUCTING LINES
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Patent #:
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|
Issue Dt:
|
03/26/1985
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Application #:
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06397052
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Filing Dt:
|
07/12/1982
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Title:
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PROCESS FOR AND STRUCTURE OF HIGH DENSITY VLSI CIRCUITS, HAVING SELF- ALIGNED GATES AND CONTACTS FOR PET DEVICES AND CONDUCTING LINES
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Patent #:
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Issue Dt:
|
07/17/1984
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Application #:
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06397646
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Filing Dt:
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07/12/1982
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Title:
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HIGH RATE RESIST POLYMERIZATION APPARATUS
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Patent #:
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Issue Dt:
|
04/24/1984
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Application #:
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06456183
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Filing Dt:
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01/06/1983
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Title:
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REACTIVE ION ETCHING OF MOLTYBDENUM SILICIDE AND N POLYSILICON
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Patent #:
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Issue Dt:
|
01/27/1987
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Application #:
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06484666
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Filing Dt:
|
04/13/1983
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Title:
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DIMENSION MONITORING TECHNIQUE FOR SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
|
04/02/1985
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Application #:
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06531529
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Filing Dt:
|
09/12/1983
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Title:
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METHOD FOR MAKING A RELIABLE OHMIC CONTACT BETWEEN TWO LAYERS OF INTEGRATED CIRCUIT METALLIZATIONS
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Patent #:
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Issue Dt:
|
02/05/1985
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Application #:
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06544914
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Filing Dt:
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10/24/1983
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Title:
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SMALL AREA HIGH VALUE RESISTOR WITH GREATLY REDUCED PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
|
06/10/1986
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Application #:
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06621773
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Filing Dt:
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06/18/1984
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Title:
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TWO-LEVEL TRANSISTOR STRUCTURES AND METHOD UTILIZING MINIMAL AREA THEREFOR
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Patent #:
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Issue Dt:
|
07/09/1991
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Application #:
|
07062007
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Filing Dt:
|
06/12/1987
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Title:
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LATERAL TRANSISTOR SEPARATED FROM SUBSTRATE BY INTERSECTING SLOTS FILLED WITH SUBSTRATE OXIDE FOR MINIMAL INTERFERENCE THEREFROM
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Patent #:
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Issue Dt:
|
03/17/1992
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Application #:
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07068383
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Filing Dt:
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06/11/1987
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Title:
|
COMPLEMENTARY NPN AND PNP LATERAL TRANSISTORS SEPARATED FROM SUBSTRATE BY INTERSECTING SLOTS FILLED WITH SUBSTRATE OXIDE FOR MINIMAL INTERFERENCE THEREFROM
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Patent #:
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Issue Dt:
|
05/23/2006
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Application #:
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09575055
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Filing Dt:
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05/19/2000
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Title:
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METHOD FOR SELECTIVE FABRICATION OF HIGH CAPACITANCE DENSITY AREAS IN A LOW DIELECTRIC CONSTANT MATERIAL
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Patent #:
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Issue Dt:
|
02/07/2006
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Application #:
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09590462
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Filing Dt:
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06/09/2000
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Title:
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DOUBLE-IMPLANT HIGH PERFORMANCE VARACTOR AND METHOD FOR MANUFACTURING SAME
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Patent #:
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Issue Dt:
|
01/10/2006
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Application #:
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09665422
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Filing Dt:
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09/20/2000
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Title:
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DAMASCENE INTERCONNECT STRUCTURE AND FABRICATION METHOD HAVING AIR GAPS BETWEEN METAL LINES AND METAL LAYERS
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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09686323
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Filing Dt:
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10/09/2000
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Title:
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METHOD OF FABRICATING AN INTERCONNECT STRUCTURE EMPLOYING AIR GAPS BETWEEN METAL LINES AND BETWEEN METAL LAYERS
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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09754806
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Filing Dt:
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01/02/2001
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Publication #:
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Pub Dt:
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01/31/2002
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Title:
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ON-CHIP INDUCTORS
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Patent #:
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Issue Dt:
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05/15/2007
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Application #:
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09833953
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Filing Dt:
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04/11/2001
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Publication #:
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Pub Dt:
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10/17/2002
| | | | |
Title:
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LOW COST FABRICATION OF HIGH RESISTIVITY RESISTORS
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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10054438
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Filing Dt:
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01/22/2002
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Publication #:
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Pub Dt:
|
07/11/2002
| | | | |
Title:
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INDEPENDENT CONTROL OF POLYCRYSTALLINE SILICON-GERMANIUM IN AN HBT AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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10075701
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Filing Dt:
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02/14/2002
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Title:
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METHOD FOR CONTROLLING AN EMITTER WINDOW OPENING IN AN HBT AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10190297
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Filing Dt:
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07/05/2002
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Title:
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FABRICATION OF HIGH-DENSITY CAPACITORS FOR MIXED SIGNAL/RF CIRCUITS
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Patent #:
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Issue Dt:
|
01/04/2005
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Application #:
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10190459
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Filing Dt:
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07/05/2002
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Title:
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DAMASCENE TRENCH CAPACITOR FOR MIXED-SIGNAL/RF IC APPLICATIONS
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Patent #:
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Issue Dt:
|
12/06/2005
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Application #:
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10313583
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Filing Dt:
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12/07/2002
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Title:
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Efficiently fabricated bipolar transistor
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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10321877
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Filing Dt:
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12/17/2002
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Title:
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POLYCRYSTALLINE SILICON EMITTER HAVING AN ACCURATELY CONTROLLED CRITICAL DIMENSION
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10371307
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Filing Dt:
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02/20/2003
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Title:
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METHOD FOR FORMING DEEP TRENCH ISOLATION AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10434961
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Filing Dt:
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05/09/2003
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Title:
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TECHNIQUE FOR REDUCING CONTAMINANTS IN FABRICATION OF SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10442449
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Filing Dt:
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05/21/2003
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Publication #:
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Pub Dt:
|
07/15/2004
| | | | |
Title:
|
METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10712067
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Filing Dt:
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11/13/2003
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Title:
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METHOD FOR FABRICATING A HIGH DENSITY COMPOSITE MIM CAPACITOR WITH REDUCED VOLTAGE DEPENDENCE IN SEMICONDUCTOR DIES
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10758494
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Filing Dt:
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01/15/2004
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Title:
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CIRCUIT FOR DETECTING ARCING IN AN ETCH TOOL DURING WAFER PROCESSING
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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10826507
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Filing Dt:
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04/16/2004
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Title:
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COMPOSITE GROUND SHIELD FOR PASSIVE COMPONENTS IN A SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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10842943
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Filing Dt:
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05/10/2004
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Title:
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DEEP TRENCH ISOLATION REGION WITH REDUCED-SIZE CAVITIES IN OVERLYING FIELD OXIDE
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10843190
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Filing Dt:
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05/10/2004
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Title:
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COMPOSITE SERIES RESISTOR HAVING REDUCED TEMPERATURE SENSITIVITY IN AN IC CHIP
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10850187
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Filing Dt:
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05/19/2004
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Title:
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METHOD FOR FABRICATING A HIGH DENSITY COMPOSITE MIM CAPACITOR WITH FLEXIBLE ROUTING IN SEMICONDUCTOR DIES
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10865153
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Filing Dt:
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06/09/2004
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING RECESSED SPACERS
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10865634
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Filing Dt:
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06/10/2004
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Title:
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NPN TRANSISTOR HAVING REDUCED EXTRINISIC BASE RESISTANCE AND IMPROVED MANUFACTURABILITY
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10870900
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Filing Dt:
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06/17/2004
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10888406
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Filing Dt:
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07/10/2004
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Title:
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TRANSISTOR EMITTER HAVING ALTERNATING UNDOPED AND DOPED LAYERS
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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10892015
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Filing Dt:
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07/14/2004
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Title:
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BIPOLAR TRANSISTOR FABRICATED IN A BICMOS PROCESS
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Patent #:
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Issue Dt:
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11/07/2006
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Application #:
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10915797
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Filing Dt:
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08/11/2004
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Title:
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SIGE LAYER HAVING SMALL POLY GRAINS
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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10936927
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Filing Dt:
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09/09/2004
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Title:
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CMOS TRANSISTOR SPACERS FORMED IN A BICMOS PROCESS
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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10952256
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Filing Dt:
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09/28/2004
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Title:
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METHOD FOR FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR WITHOUT SPACERS
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Patent #:
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Issue Dt:
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03/04/2008
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Application #:
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10970645
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Filing Dt:
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10/20/2004
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Title:
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METHOD FOR OPTO-ELECTRONIC INTEGRATION ON A SOI SUBSTRATE AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10995762
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Filing Dt:
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11/22/2004
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Title:
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SELECTIVE FABRICATION OF HIGH CAPACITANCE DENSITY AREAS IN A LOW DIELECTRIC CONSTANT MATERIAL
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10995769
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Filing Dt:
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11/22/2004
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Title:
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SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY
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Patent #:
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Issue Dt:
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11/20/2007
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Application #:
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10997534
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11/23/2004
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Title:
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METHOD AND STRUCTURE FOR INTEGRATION OF PHOSPHORUS EMITTER IN AN NPN DEVICE IN A BICMOS PROCESS
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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10997638
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11/23/2004
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Publication #:
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Pub Dt:
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05/25/2006
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Title:
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METHOD FOR FABRICATING A MIM CAPACITOR HAVING INCREASED CAPACITANCE DENSITY AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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11003572
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Filing Dt:
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12/02/2004
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Title:
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NPN TRANSISTOR HAVING REDUCED EXTRINSIC BASE RESISTANCE AND IMPROVED MANUFACTURABILITY
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Patent #:
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Issue Dt:
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03/04/2008
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Application #:
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11018164
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Filing Dt:
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12/20/2004
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Title:
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SOI SUBSTRATE FOR INTEGRATION OF OPTO-ELECTRONICS WITH SIGE BICMOS
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Patent #:
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Issue Dt:
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06/02/2009
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Application #:
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11084391
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03/17/2005
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Title:
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INTEGRATION OF SIGE NPN AND VERTICAL PNP DEVICES ON A SUBSTRATE
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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11086168
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Filing Dt:
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03/21/2005
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Title:
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METHOD FOR EFFECTIVE BICMOS PROCESS INTEGRATION
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Patent #:
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Issue Dt:
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05/04/2010
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Application #:
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11112194
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04/22/2005
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Publication #:
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Pub Dt:
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10/01/2009
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Title:
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DENSELY PACKED METAL SEGMENTS PATTERNED IN A SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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11121360
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05/03/2005
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Publication #:
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Pub Dt:
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11/09/2006
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Title:
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METHOD FOR FABRICATING A MIM CAPACITOR HIGH-K DIELECTRIC FOR INCREASED CAPACITANCE DENSITY AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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11/06/2007
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Application #:
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11146537
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Filing Dt:
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06/06/2005
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Title:
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SELECTIVE AND NON-SELECTIVE EPITAXY FOR BASE INTEGRATION IN A BICMOS PROCESS AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
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11/06/2007
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Application #:
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11175720
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Filing Dt:
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07/06/2005
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Title:
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FABRICATING A SELF-ALIGNED BIPOLAR TRANSISTOR HAVING INCREASED MANUFACTURABILITY
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Patent #:
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Issue Dt:
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09/15/2015
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Application #:
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11198425
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Filing Dt:
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08/05/2005
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Title:
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Deep N wells in triple well structures
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Patent #:
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Issue Dt:
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03/03/2009
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Application #:
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11525457
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Filing Dt:
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09/21/2006
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Title:
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INTEGRATION OF PHOSPHORUS EMITTER IN AN NPN DEVICE IN A BICMOS PROCESS
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Patent #:
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07/03/2012
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11542088
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10/02/2006
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Title:
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STRUCTURE FOR ENCAPSULATING MICROELECTRONIC DEVICES
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Issue Dt:
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04/27/2010
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11641500
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12/18/2006
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Title:
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METHOD FOR FABRICATING A FRONTSIDE THROUGH-WAFER VIA IN A PROCESSED WAFER AND RELATED STRUCTURE
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Issue Dt:
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09/15/2009
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11641925
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12/18/2006
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Title:
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METHOD FOR FABRICATING A TOP CONDUCTIVE LAYER IN A SEMICONDUCTOR DIE AND RELATED STRUCTURE
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