Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 035056/0299 | |
| Pages: | 5 |
| | Recorded: | 02/27/2015 | | |
| Attorney Dkt #: | 22272-26602/US |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
3
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Patent #:
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Issue Dt:
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12/26/2017
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Application #:
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14628105
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Filing Dt:
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02/20/2015
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Publication #:
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Pub Dt:
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08/25/2016
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Title:
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Memory Optimization in VLSI Design Using Generic Memory Models
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Patent #:
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Issue Dt:
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08/08/2017
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Application #:
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14628668
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Filing Dt:
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02/23/2015
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Publication #:
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Pub Dt:
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08/25/2016
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Title:
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Generating Specific Memory Models Using Generic Memory Models for Designing Memories in VLSI Design
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Patent #:
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Issue Dt:
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08/08/2017
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Application #:
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14628676
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Filing Dt:
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02/23/2015
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Publication #:
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Pub Dt:
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08/25/2016
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Title:
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Designing Memories in VLSI Design Using Specific Memory Models Generated from Generic Memory Models
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Assignee
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| 2130 GOLD STREET |
| STE. 100 |
| SAN JOSE, CALIFORNIA 95002 |
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Correspondence name and address
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FENWICK & WEST LLP
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801 CALIFORNIA STREET
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MOUNTAIN VIEW, CA 94041
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