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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08799074
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Filing Dt:
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02/11/1997
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Title:
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HIGH-VOLTAGE CMOS LEVEL SHIFTER
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Patent #:
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Issue Dt:
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09/01/1998
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Application #:
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08808237
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Filing Dt:
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02/28/1997
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Title:
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HIGH VOLTAGE NMOS PASS GATE FOR INTEGRATED CIRCUIT WITH HIGH VOLTAGE GENERATOR
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Patent #:
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Issue Dt:
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06/15/1999
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Application #:
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08940674
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Filing Dt:
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09/30/1997
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Title:
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A DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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09063688
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Filing Dt:
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04/21/1998
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Title:
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DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09109664
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Filing Dt:
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07/02/1998
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Title:
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LOW VOLTAGE JUNCTION AND HIGH VOLTAGE JUNCTION OPTIMIZATION FOR FLASH MEMORY
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09109755
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Filing Dt:
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07/02/1998
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Title:
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SHALLOW TRENCH ISOLATION PROCESS PARTICULARLY SUITED FOR HIGH VOLTAGE CIRCUITS
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09128024
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Filing Dt:
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08/03/1998
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Title:
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VT REFERENCE VOLTAGE FOR EXTREMELY LOW POWER SUPPLY
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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09159023
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Filing Dt:
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09/23/1998
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Title:
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METHOD OF MAKING FLEXIBLY PARTITIONED METAL LINE SEGMENTS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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Patent #:
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Issue Dt:
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12/21/1999
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Application #:
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09159342
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Filing Dt:
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09/23/1998
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Title:
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MEMORY ADDRESS DECODING CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09159489
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Filing Dt:
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09/23/1998
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Title:
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BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09166385
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Filing Dt:
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10/05/1998
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Title:
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WORDLINE DRIVER FOR FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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09175646
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Filing Dt:
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10/20/1998
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Title:
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SCHEME FOR PAGE ERASE AND ERASE VERIFY IN A NON -VOLATILE MEMORY ARRAY
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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09175647
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Filing Dt:
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10/20/1998
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Title:
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BIT LINE BIASING METHOD TO ELIMATE PROGRAM DISTURBANCE IN A NON-VOLATILE MEMORY DEVICE AND MEMORY DEVICE EMPLOYING THE SAME
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09283308
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Filing Dt:
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03/31/1999
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Title:
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BARRIER LAYER DECREASES NITROGEN CONTAMINATION OF PERIPHERAL GATE REGIONS DURING TUNNEL OXIDE NITRIDATION
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09309994
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Filing Dt:
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05/11/1999
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Title:
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CORE FIELD ISOLATION FOR A NAND FLASH MEMORY
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09410512
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Filing Dt:
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09/30/1999
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Title:
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DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09419695
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Filing Dt:
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10/14/1999
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Title:
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METHOD AND SYSTEM FOR SAVING OVERHEAD PROGRAM TIME IN A MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09421105
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Filing Dt:
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10/19/1999
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Title:
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SECTOR WRITE PROTECT CAMS FOR A SIMULTANEOUS OPERATION FLASH MEMORY
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09421142
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Filing Dt:
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10/19/1999
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Title:
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LATCHING CAM DATA IN A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09421470
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Filing Dt:
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10/19/1999
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Title:
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ARRAY VT MODE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09421471
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Filing Dt:
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10/19/1999
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Title:
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OUTPUT SWITCHING IMPLEMENTATION FOR A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09421757
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Filing Dt:
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10/19/1999
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Title:
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WRITE PROTECT INPUT IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09421758
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Filing Dt:
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10/19/1999
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Title:
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MULTIPLE PURPOSE BUS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09421774
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Filing Dt:
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10/19/1999
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Title:
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COMMON FLASH INTERFACE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09421775
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Filing Dt:
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10/19/1999
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Title:
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REFERENCE CELL BITLINE PATH ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09421776
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Filing Dt:
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10/19/1999
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Title:
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ADDRESS TRANSISTION DETECT TIMING ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09421984
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Filing Dt:
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10/19/1999
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Title:
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REFERENCE CELL FOUR-WAY SWITCH FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09421985
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Filing Dt:
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10/19/1999
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Title:
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LOW VOLTAGE READ CASCODE FOR 2V/3V AND DIFFERENT BANK COMBINATIONS WITHOUT METAL OPTIONS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09422198
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Filing Dt:
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10/19/1999
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Title:
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SENSE AMPLIFIER ARCHITECTURE FOR SLIDING BANKS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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|
Issue Dt:
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09/12/2000
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Application #:
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09422199
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Filing Dt:
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10/19/1999
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Title:
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OUTPUT MULTIPLEXING IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09426205
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FABRICATING A BIT-LINE IN A MONOS DEVICE USING A DUAL LAYER HARD MASK
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09426239
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Filing Dt:
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10/25/1999
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Title:
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METHOD TO GENERATE A MONOS TYPE FLASH CELL USING POLYCRYSTALLINE SILICON AS AN ONO TOP LAYER
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09426430
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Filing Dt:
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10/25/1999
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Title:
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METHOD OF FABRICATING AN ONO DIELECTRIC BY NITRIDATION FOR MNOS MEMORY CELLS
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09426672
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Filing Dt:
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10/25/1999
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Title:
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HIGH TEMPERATURE OXIDE DEPOSITION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO BIT EEPROM DEVICE
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09427402
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Filing Dt:
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10/25/1999
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Title:
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INTEGRATED METHOD BY USING HIGH TEMPERATURE OXIDE FOR TOP OXIDE AND PERIPHERY GATE OXIDE
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09427404
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FABRICATING A BIT-LINE USING BURIED DIFFUSION ISOLATION
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09429244
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Filing Dt:
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10/28/1999
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Title:
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METHOD AND SYSTEM FOR PROVIDINNG A POLYSILICON STRINGER MONITOR
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09431296
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Filing Dt:
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10/29/1999
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Title:
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FLASH MEMORY WORDLINE TRACKING ACROSS WHOLE CHIP
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09490340
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Filing Dt:
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01/24/2000
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Title:
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Distributed voltage charge circuits to reduce sensing time in a memory device
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09492353
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Filing Dt:
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01/27/2000
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Title:
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Two bit flash cell with two floating gate regions
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Patent #:
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|
Issue Dt:
|
06/05/2001
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Application #:
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09501159
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Filing Dt:
|
02/09/2000
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Title:
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Voltage boost reset circuit for a flash memory
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Patent #:
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|
Issue Dt:
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05/29/2001
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Application #:
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09526239
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Filing Dt:
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03/15/2000
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Title:
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Multiple bank simultaneous operation for a flash memory
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Patent #:
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|
Issue Dt:
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11/12/2002
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Application #:
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09532347
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Filing Dt:
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03/21/2000
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Title:
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METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE USING HIGH TEMPERATURE DESCUM
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Patent #:
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|
Issue Dt:
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08/13/2002
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Application #:
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09535255
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Filing Dt:
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03/23/2000
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Title:
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METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE LAYERS BY REDUCING DESCUM INDUCED DEFECTS
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Patent #:
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|
Issue Dt:
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10/08/2002
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Application #:
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09535256
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Filing Dt:
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03/23/2000
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Publication #:
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|
Pub Dt:
|
05/16/2002
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Title:
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METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE LAYERS BY REDUCING DESCUM INDUCED DEFECTS
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Patent #:
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|
Issue Dt:
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03/27/2001
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Application #:
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09547556
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Filing Dt:
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04/12/2000
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Title:
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Address transition detect timing architecture for a simultaneous operation flash memory device
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09558764
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Filing Dt:
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04/26/2000
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Title:
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Apparatus and method to characterize the threshold distribution in an nrom virtual ground array
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09593303
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Filing Dt:
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06/13/2000
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Title:
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Method to reduce capactive loading in flash memory x-decoder for accurate voltage control at wordlines and select lines
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09595519
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Filing Dt:
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06/16/2000
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Title:
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Voltage boost level clamping circuit for a flash memory
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Patent #:
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|
Issue Dt:
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05/28/2002
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Application #:
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09632390
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Filing Dt:
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08/04/2000
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Title:
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REDUNDANT DUAL BANK ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
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Patent #:
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|
Issue Dt:
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05/08/2001
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Application #:
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09638055
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Filing Dt:
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08/11/2000
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Title:
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Burst read mode word line boosting
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Patent #:
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|
Issue Dt:
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12/04/2001
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Application #:
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09644358
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Filing Dt:
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08/23/2000
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Title:
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Precise reference wordline loading compensation for a high density flash memory device
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09648077
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Filing Dt:
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08/25/2000
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Title:
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METHOD OF FORMING ONO FLASH MEMORY DEVICES USING RAPID THERMAL OXIDATION
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09648361
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Filing Dt:
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08/25/2000
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Title:
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METHOD OF FORMING ONO FLASH MEMORY DEVICES USING LOW ENERGY NITROGEN IMPLANTATION
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09649027
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Filing Dt:
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08/28/2000
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Title:
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METHOD OF MAKING TUNGSTEN GATE MOS TRANSISTOR AND MEMORY CELL BY ENCAPSULATING
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09651684
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Filing Dt:
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08/30/2000
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Title:
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Semiconductor structure
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09652136
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Filing Dt:
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08/31/2000
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Title:
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NON-VOLATILE MEMORY DEVICE WITH ENCAPSULATED TUNGSTEN GATE AND METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09652742
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Filing Dt:
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08/31/2000
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Title:
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Method and apparatus for eliminating false data in a page mode memory device
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09661356
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Filing Dt:
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09/14/2000
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Title:
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Output buffer for external voltage
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09661358
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Filing Dt:
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09/14/2000
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Title:
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Chip enable input buffer
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Patent #:
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Issue Dt:
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03/05/2002
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Application #:
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09663552
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Filing Dt:
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09/18/2000
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Title:
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System and method for tracking sensing speed by an equalization pulse for a high density flash memory device
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09663765
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Filing Dt:
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09/18/2000
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Title:
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VARIABLE SECTOR SIZE FOR A HIGH DENSITY FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09663909
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Filing Dt:
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09/18/2000
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Title:
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Address transition detector architecture for a high density flash memory device
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09667891
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Filing Dt:
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09/22/2000
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Title:
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Application of external voltage during array VT testing
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09668100
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Filing Dt:
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09/22/2000
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Title:
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NEGATIVE VOLTAGE REGULATION
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09675372
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Filing Dt:
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09/29/2000
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Title:
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POWER-SAVING MODES FOR MEMORIES
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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09676623
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Filing Dt:
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10/02/2000
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Title:
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I/O BASED COLUMN REDUNDANCY FOR VIRTUAL GROUND WITH 2-BIT CELL FLASH MEMORY
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09676902
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Filing Dt:
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10/02/2000
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Title:
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Architecture for a dual-bank page mode memory with redundancy
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09680344
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Filing Dt:
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10/05/2000
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Title:
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Wordline driver for flash memory read mode
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09688936
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Filing Dt:
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10/16/2000
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Title:
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SIDEWALL NROM AND METHOD OF MANUFACTURE THEREOF FOR NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09689036
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Filing Dt:
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10/12/2000
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Title:
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Two side decoding of a memory array
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09690554
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Filing Dt:
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10/17/2000
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Title:
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Word line decoding architecture in a flash memory
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09691643
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Filing Dt:
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10/18/2000
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Title:
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METHOD OF FORMING NARROW INSULATING SPACERS FOR USE IN REDUCING MINIMUM COMPONENT SIZE
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09698614
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Filing Dt:
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10/27/2000
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Title:
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MEMORY LINE DISCHARGE BEFORE SENSING
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09712382
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Filing Dt:
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11/13/2000
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Title:
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Acceleration voltage implementation for a high density flash memory device
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09723635
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Filing Dt:
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11/28/2000
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Title:
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SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09723653
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Filing Dt:
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11/28/2000
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Title:
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METHOD OF SIMULTANEOUS FORMATION OF BITLINE ISOLATION AND PERIPHEY OXIDE
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09724675
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Filing Dt:
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11/28/2000
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Title:
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MULTI-SET BLOCK ERASE
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09729388
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Filing Dt:
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12/04/2000
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Publication #:
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Pub Dt:
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12/13/2001
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Title:
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POWER SAVING SCHEME FOR BURST MODE IMPLEMENTATION DURING READING OF DATA FROM A MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09772600
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Filing Dt:
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01/30/2001
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Title:
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FLASH MEMORY ERASE SPEED BY FLUORINE IMPLANT OR FLUORINATION
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09798667
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Filing Dt:
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03/02/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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09809969
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Filing Dt:
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03/16/2001
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Title:
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DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09810155
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Filing Dt:
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03/16/2001
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Title:
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PROCESS FOR MAKING A DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
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Patent #:
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Issue Dt:
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05/07/2002
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Application #:
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09822995
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Filing Dt:
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03/30/2001
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Title:
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I/O partitioning system and methodology to reduce band-to-band tunneling current during erase
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09829193
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Filing Dt:
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04/09/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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SOFT PROGRAM AND SOFT PROGRAM VERIFY OF THE CORE CELLS IN FLASH MEMORY ARRAY
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09829518
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Filing Dt:
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04/09/2001
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Publication #:
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Pub Dt:
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01/31/2002
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Title:
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BURST ARCHITECTURE FOR A FLASH MEMORY
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09873927
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Filing Dt:
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06/04/2001
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Title:
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METHODS AND APPARATUS FOR READING A CAM CELL USING BOOSTED AND REGULATED GATE VOLTAGE
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09884583
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Filing Dt:
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06/19/2001
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Title:
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Ceiling test mode to characterize the threshold voltage distribution of over programmed memory cells
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Patent #:
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Issue Dt:
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10/14/2003
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Application #:
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09892431
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Filing Dt:
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06/26/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09893279
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Filing Dt:
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06/27/2001
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Title:
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SOURCE DRAIN IMPLANT DURING ONO FORMATION FOR IMPROVED ISOLATION OF SONOS DEVICES
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09915018
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Filing Dt:
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07/25/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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VOLTAGE BOOST CIRCUIT USING SUPPLY VOLTAGE DETECTION TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS IN READ MODE VOLTAGES
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09928059
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Filing Dt:
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08/10/2001
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Title:
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DECODER APPARATUS AND METHODS FOR PRE-CHARGING BIT LINES
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09998624
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Filing Dt:
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11/30/2001
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Title:
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DIE SEAL FOR SEMICONDUCTOR DEVICE MOISTURE PROTECTION
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09999869
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Filing Dt:
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10/23/2001
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Title:
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DRAIN SIDE SENSING SCHEME FOR VIRTUAL GROUND FLASH EPROM ARRAY WITH ADJACENT BIT CHARGE AND HOLD
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10022798
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Filing Dt:
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12/20/2001
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Publication #:
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Pub Dt:
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06/26/2003
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Title:
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MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10045354
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Filing Dt:
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11/07/2001
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Title:
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INNOVATIVE METHOD OF HARD MASK REMOVAL
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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10061620
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Filing Dt:
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02/01/2002
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Publication #:
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Pub Dt:
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06/13/2002
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Title:
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POWER-SAVING MODES FOR MEMORIES
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10086112
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Filing Dt:
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02/27/2002
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Title:
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NROM CELL WITH N-LESS CHANNEL
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10100485
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Filing Dt:
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03/14/2002
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10109234
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Filing Dt:
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03/27/2002
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Title:
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LINER FOR SEMICONDUCTOR MEMORIES AND MANUFACTURING METHOD THEREFOR
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