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Total properties:
30
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Patent #:
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Issue Dt:
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05/25/1999
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Application #:
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09049517
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Filing Dt:
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03/27/1998
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Title:
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PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT WITH A SELF-ALIGNED CONTACT
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Patent #:
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Issue Dt:
|
02/13/2001
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Application #:
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09193252
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Filing Dt:
|
11/17/1998
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Title:
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SEMICONDUCTOR DEVICE MANUFACTURING METHOD INCLUDING VARIOUS OXIDATION STEPS WITH DIFFERENT CONCENTRATION OF CHLORINE TO FORM A FIELD OXIDE
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Patent #:
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Issue Dt:
|
09/03/2002
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Application #:
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09318429
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Filing Dt:
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05/25/1999
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Title:
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PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT WITH A SELF-ALIGNED CONTACT
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Patent #:
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Issue Dt:
|
08/21/2001
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Application #:
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09359652
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Filing Dt:
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07/26/1999
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Title:
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BRAIN COOLING APPARATUS AND METHOD FOR COOLING THE BRAIN
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Patent #:
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Issue Dt:
|
09/04/2001
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Application #:
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09562747
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Filing Dt:
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05/02/2000
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Title:
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Decoded source lines to tighten erase Vt distribution
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Patent #:
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Issue Dt:
|
06/17/2003
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Application #:
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09726384
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Filing Dt:
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12/01/2000
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Publication #:
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Pub Dt:
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04/12/2001
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Title:
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SEMICONDUCTOR DEVICE MANUFACTURING METHOD
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|
|
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Patent #:
|
|
Issue Dt:
|
08/05/2008
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Application #:
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10928665
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Filing Dt:
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08/27/2004
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Title:
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SEMICONDUCTOR COMPONENT HAVING A CONTACT STRUCTURE AND METHOD OF MANUFACTURE
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Patent #:
|
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Issue Dt:
|
11/14/2006
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Application #:
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10939775
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Filing Dt:
|
09/13/2004
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Title:
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METHOD OF MAKING A SEMICONDUCTOR STRUCTURE
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|
|
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Patent #:
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Issue Dt:
|
06/26/2007
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Application #:
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10976876
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Filing Dt:
|
11/01/2004
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Title:
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SEMICONDUCTOR DEVICE WITH ELECTRICALLY BIASED DIE EDGE SEAL
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|
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Patent #:
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|
Issue Dt:
|
06/19/2007
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Application #:
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10988239
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Filing Dt:
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11/12/2004
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Title:
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UTILIZATION OF A TA-CONTAINING CAP OVER COPPER TO FACILITATE CONCURRENT FORMATION OF COPPER VIAS AND MEMORY ELEMENT STRUCTURES
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Patent #:
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Issue Dt:
|
10/30/2007
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Application #:
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11000870
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Filing Dt:
|
12/01/2004
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Title:
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METAL/OXIDE ETCH AFTER POLISH TO PREVENT BRIDGING BETWEEN ADJACENT FEATURES OF A SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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12/18/2007
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Application #:
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11065388
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Filing Dt:
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02/24/2005
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Title:
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MEMORY DEVICE HAVING A NANOCRYSTAL CHARGE STORAGE REGION AND METHOD
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Patent #:
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Issue Dt:
|
08/19/2008
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Application #:
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11112884
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Filing Dt:
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04/22/2005
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Title:
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MEMORY CELL HAVING COMBINATION RAISED SOURCE AND DRAIN AND METHOD OF FABRICATING SAME
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|
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Patent #:
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|
Issue Dt:
|
08/14/2007
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Application #:
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11135492
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Filing Dt:
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05/24/2005
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|
Title:
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INTERFACE LAYER BETWEEN DUAL POLYCRYSTALLINE SILICON LAYERS
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Patent #:
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Issue Dt:
|
07/26/2011
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Application #:
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11186969
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Filing Dt:
|
07/22/2005
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|
Title:
|
SYSTEM AND METHOD FOR IMPROVING RELIABILITY IN A SEMICONDUCTOR DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
11/30/2010
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Application #:
|
11193409
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Filing Dt:
|
08/01/2005
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|
Publication #:
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Pub Dt:
|
02/01/2007
| | | | |
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Title:
|
SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/19/2011
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Application #:
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11235214
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Filing Dt:
|
09/27/2005
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|
Publication #:
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Pub Dt:
|
03/29/2007
| | | | |
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Title:
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METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/12/2014
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Application #:
|
11277008
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Filing Dt:
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03/20/2006
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Publication #:
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Pub Dt:
|
09/20/2007
| | | | |
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Title:
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MEMORY CELL SYSTEM USING SILICON-RICH NITRIDE
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Patent #:
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Issue Dt:
|
08/09/2011
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Application #:
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11286173
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Filing Dt:
|
11/22/2005
|
|
Title:
|
INTEGRATED CIRCUIT CONTACT SYSTEM
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|
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Patent #:
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|
Issue Dt:
|
05/19/2009
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Application #:
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11356311
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Filing Dt:
|
02/17/2006
|
|
Title:
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SEMICONDUCTOR DEVICES WITH COPPER INTERCONNECTS AND COMPOSITE SILICON NITRIDE CAPPING LAYERS
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Patent #:
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|
Issue Dt:
|
03/03/2009
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Application #:
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11371024
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Filing Dt:
|
03/09/2006
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|
Title:
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ENHANCED ETCHING OF A HIGH DIELECTRIC CONSTANT LAYER
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|
|
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Patent #:
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|
Issue Dt:
|
04/15/2008
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Application #:
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11388390
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Filing Dt:
|
03/24/2006
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|
Title:
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METHOD FOR DECREASING SHEET RESISTIVITY VARIATIONS OF AN INTERCONNECT METAL LAYER
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/13/2010
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Application #:
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11412365
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Filing Dt:
|
04/26/2006
|
|
Title:
|
METHODS FOR FABRICATING FLASH MEMORY DEVICES
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|
|
|
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Patent #:
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|
Issue Dt:
|
11/19/2013
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Application #:
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11458046
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Filing Dt:
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07/17/2006
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|
Publication #:
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Pub Dt:
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01/17/2008
| | | | |
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Title:
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MEMORY CELL SYSTEM WITH CHARGE TRAP
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/27/2011
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Application #:
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11593086
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Filing Dt:
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11/06/2006
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Publication #:
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Pub Dt:
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05/08/2008
| | | | |
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Title:
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CU ANNEALING FOR IMPROVED DATA RETENTION IN FLASH MEMORY DEVICES
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|
|
|
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Patent #:
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|
Issue Dt:
|
10/09/2012
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Application #:
|
11611856
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Filing Dt:
|
12/16/2006
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|
Publication #:
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|
Pub Dt:
|
06/19/2008
| | | | |
|
Title:
|
INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
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Application #:
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11616563
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Filing Dt:
|
12/27/2006
|
|
Publication #:
|
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Pub Dt:
|
07/03/2008
| | | | |
|
Title:
|
METHOD FOR IMPROVED PLANARIZATION IN SEMICONDUCTOR DEVICES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/03/2013
|
Application #:
|
12910331
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Filing Dt:
|
10/22/2010
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2011
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13044313
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Filing Dt:
|
03/09/2011
|
|
Publication #:
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|
Pub Dt:
|
06/30/2011
| | | | |
|
Title:
|
METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
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13644387
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Filing Dt:
|
10/04/2012
|
|
Publication #:
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Pub Dt:
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05/23/2013
| | | | |
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Title:
|
INTEGRATED CIRCUIT WITH METAL AND SEMI-CONDUCTING GATE
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