Patent Assignment Details
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| Reel/Frame: | 017319/0318 | |
| Pages: | 3 |
| | Recorded: | 03/08/2006 | | |
| Attorney Dkt #: | 015114-079900US |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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08/19/2008
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Application #:
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11303734
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Filing Dt:
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12/16/2005
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Title:
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USING DEDICATED READ OUTPUT PATH TO REDUCE UNREGISTERED READ ACCESS TIME FOR FPGA EMBEDDED MEMORY
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Assignee
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| 101 INNOVATION DRIVE |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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JONATHAN M. HOLLADER
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TOWNSEND AND TOWNSEND AND CREW LLP
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TWO EMBARCADERO CENTER, EIGHTH FLOOR
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SAN FRANCISCO, CALIFORNIA 94111-3834
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