skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:025646/0319   Pages: 16
Recorded: 01/15/2011
Attorney Dkt #:252016-9000 (#3)
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 28
1
Patent #:
Issue Dt:
11/12/2002
Application #:
09033102
Filing Dt:
03/02/1998
Title:
CAPACITOR OVER METAL DRAM STRUCTURE
2
Patent #:
Issue Dt:
07/10/2001
Application #:
09071309
Filing Dt:
05/01/1998
Title:
METHOD FOR FORMING STORAGE NODE USING RESIST OR ANTI-REFLECTIVE MATERIAL
3
Patent #:
Issue Dt:
02/05/2002
Application #:
09192457
Filing Dt:
11/16/1998
Title:
METHODS OF MANUFACTURE OF CROWN OR STACK CAPACITOR WITH A MONOLITHIC FIN STRUCTURE MADE WITH A DIFFERENT OXIDE ETCHING RATE IN HYDROGEN FLUORIDE VAPOR
4
Patent #:
Issue Dt:
06/26/2001
Application #:
09225899
Filing Dt:
01/04/1999
Title:
METHOD OF MANUFACTURING A CUP-SHAPE CAPACITOR
5
Patent #:
Issue Dt:
05/15/2001
Application #:
09239883
Filing Dt:
01/29/1999
Title:
METHOD FOR FABRICATING A CAPACITOR
6
Patent #:
Issue Dt:
03/27/2001
Application #:
09258087
Filing Dt:
02/25/1999
Title:
METHOD FOR PREVENTING SILICON SUBSTRATE LOSS IN FABRICATING SEMICONDUCTOR DEVICE
7
Patent #:
Issue Dt:
06/19/2001
Application #:
09292128
Filing Dt:
04/14/1999
Title:
FABRICATION METHOD TO APPROACH THE CONDUCTING STRUCTURE OF A DRAM CELL WITH STRAIGHTFORWARD BIT LINE
8
Patent #:
Issue Dt:
08/07/2001
Application #:
09332424
Filing Dt:
06/14/1999
Title:
METHOD OF MANUFACTURING A STORAGE NODE HAVING FIVE POLYSILICON BARS
9
Patent #:
Issue Dt:
02/27/2001
Application #:
09358987
Filing Dt:
07/22/1999
Title:
NEW PROCESS FOR INTEGRATING HEMISPHERICAL GRAIN SILICON AND A NITRIDE-OXIDE CAPACITOR DIELECTRIC LAYER FOR A DYNAMIC RANDOM ACCESS MEMORY CAPACITOR STRUCTURE
10
Patent #:
Issue Dt:
03/04/2003
Application #:
09372623
Filing Dt:
08/12/1999
Title:
NOVEL TEST STRUCTURES FOR MEASURING DRAM CELL NODE JUNCTION LEAKAGE CURRENT
11
Patent #:
Issue Dt:
02/06/2001
Application #:
09414807
Filing Dt:
10/08/1999
Title:
METHOD OF FABRICATING A CAPACITOR UNDER BIT LINE DRAM STRUCTURE USING CONTACT HOLE LINERS
12
Patent #:
Issue Dt:
03/13/2001
Application #:
09425907
Filing Dt:
10/25/1999
Title:
GLOBAL PLANARIZATION PROCESS FOR HIGH STEP DRAM DEVICES VIA USE OF HF VAPOR ETCHING
13
Patent #:
Issue Dt:
06/19/2001
Application #:
09510436
Filing Dt:
02/21/2000
Title:
Power down system for regulated internal voltage supply in DRAM
14
Patent #:
Issue Dt:
04/30/2002
Application #:
09591454
Filing Dt:
06/12/2000
Title:
Method of forming asymmetric wells for dram cells
15
Patent #:
Issue Dt:
10/02/2001
Application #:
09595265
Filing Dt:
06/15/2000
Title:
Method of forming asymmetric source/drain for a dram cell
16
Patent #:
Issue Dt:
08/27/2002
Application #:
09604010
Filing Dt:
06/26/2000
Title:
METHOD OF FORMING THE CAPACITOR WITH HSG IN DRAM
17
Patent #:
Issue Dt:
07/17/2001
Application #:
09609266
Filing Dt:
06/30/2000
Title:
Method of manufacturing a dram capacitor with a dielectric column
18
Patent #:
Issue Dt:
08/21/2001
Application #:
09609267
Filing Dt:
06/30/2000
Title:
Method of manufacturing a dram capacitor with increased electrode surface area
19
Patent #:
Issue Dt:
10/30/2001
Application #:
09620068
Filing Dt:
07/20/2000
Title:
Method of forming the capacitor in DRAM
20
Patent #:
Issue Dt:
11/20/2001
Application #:
09620842
Filing Dt:
07/21/2000
Title:
Fabrication process for a lower electrode of a memory capacitor
21
Patent #:
Issue Dt:
10/02/2001
Application #:
09638299
Filing Dt:
08/16/2000
Title:
Fabrication method for capacitors in integrated circuits with a self-aligned contact structure
22
Patent #:
Issue Dt:
04/17/2001
Application #:
09660622
Filing Dt:
09/13/2000
Title:
Method for fabricating capacitors in semiconductor integrated circuit
23
Patent #:
Issue Dt:
03/19/2002
Application #:
09661099
Filing Dt:
09/13/2000
Title:
Making of making stacked capacitor in memory device
24
Patent #:
Issue Dt:
01/22/2002
Application #:
09678639
Filing Dt:
10/03/2000
Title:
Method of forming a DRAM cell
25
Patent #:
Issue Dt:
11/04/2003
Application #:
09866468
Filing Dt:
05/29/2001
Publication #:
Pub Dt:
01/31/2002
Title:
A METHOD FOR FORMING A DIELECTRIC-CONSTANT-ENCHANCED CAPACITOR
26
Patent #:
Issue Dt:
11/05/2002
Application #:
09882684
Filing Dt:
06/18/2001
Publication #:
Pub Dt:
10/18/2001
Title:
CROWN OR STACK CAPACITOR WITH A MONOLITHIC FIN STRUCTURE
27
Patent #:
Issue Dt:
04/29/2003
Application #:
09883155
Filing Dt:
06/18/2001
Publication #:
Pub Dt:
10/25/2001
Title:
METHOD OF MANUFACTURE OF A CROWN OR STACK CAPACITOR WITH A MONOLITHIC FIN STRUCTURE MADE WITH A DIFFERENT OXIDE ETCHING RATE IN HYDROGEN FLUORIDE VAPOR
28
Patent #:
Issue Dt:
01/07/2003
Application #:
10012472
Filing Dt:
12/12/2001
Title:
METHOD OF MAKING IN HIGH DENSITY DRAM CIRCUIT
Assignor
1
Exec Dt:
10/26/2010
Assignee
1
NO. 8, LI-HSIN RD. 6, SCIENCE-BASED INDUSTRIAL PARK
HSIN-CHU, TAIWAN 300-77
Correspondence name and address
THOMAS, KAYDEN, HORSTEMEYER & RISLEY
600 GALLERIA PKWY
SUITE 1500
ATLANTA, GA 30339

Search Results as of: 05/29/2024 11:34 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT