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Reel/Frame:036905/0327   Pages: 7
Recorded: 10/28/2015
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 34
1
Patent #:
5969552
Issue Dt:
10/19/1999
Application #:
09007707
Filing Dt:
01/15/1998
Title:
DUAL LOOP DELAY-LOCKED LOOP
2
Patent #:
6219747
Issue Dt:
04/17/2001
Application #:
09226776
Filing Dt:
01/06/1999
Title:
METHODS AND APPARATUS FOR VARIABLE LENGTH SDRAM TRANSFERS
3
Patent #:
6393505
Issue Dt:
05/21/2002
Application #:
09227502
Filing Dt:
01/06/1999
Title:
METHODS AND APPARATUS FOR DATA BUS ARBITRATION
4
Patent #:
6326826
Issue Dt:
12/04/2001
Application #:
09574571
Filing Dt:
05/17/2000
Title:
Wide frequency-range delay-locked loop circuit
5
Patent #:
6385692
Issue Dt:
05/07/2002
Application #:
09805588
Filing Dt:
03/12/2001
Publication #:
US20020007435
Pub Dt:
01/17/2002
Title:
METHODS AND APPARATUS FOR VARIABLE LENGTH SDRAM TRANSFERS
6
Patent #:
7154905
Issue Dt:
12/26/2006
Application #:
10035911
Filing Dt:
11/07/2001
Publication #:
US20040004975
Pub Dt:
01/08/2004
Title:
METHOD AND SYSTEM FOR NESTING OF COMMUNICATIONS PACKETS
7
Patent #:
6976201
Issue Dt:
12/13/2005
Application #:
10036794
Filing Dt:
11/07/2001
Publication #:
US20020157054
Pub Dt:
10/24/2002
Title:
METHOD AND SYSTEM FOR HOST HANDLING OF COMMUNICATIONS ERRORS
8
Patent #:
7257129
Issue Dt:
08/14/2007
Application #:
10045297
Filing Dt:
11/07/2001
Publication #:
US20020191475
Pub Dt:
12/19/2002
Title:
MEMORY ARCHITECTURE WITH MULTIPLE SERIAL COMMUNICATIONS PORTS
9
Patent #:
7039121
Issue Dt:
05/02/2006
Application #:
10045393
Filing Dt:
11/07/2001
Publication #:
US20030210162
Pub Dt:
11/13/2003
Title:
METHOD AND SYSTEM FOR TRANSITION-CONTROLLED SELECTIVE BLOCK INVERSION COMMUNICATIONS
10
Patent #:
6771192
Issue Dt:
08/03/2004
Application #:
10045600
Filing Dt:
11/07/2001
Title:
METHOD AND SYSTEM FOR DC-BALANCING AT THE PHYSICAL LAYER
11
Patent #:
7340558
Issue Dt:
03/04/2008
Application #:
10045601
Filing Dt:
11/07/2001
Publication #:
US20030208655
Pub Dt:
11/06/2003
Title:
MULTISECTION MEMORY BANK SYSTEM
12
Patent #:
7746798
Issue Dt:
06/29/2010
Application #:
10045625
Filing Dt:
11/07/2001
Publication #:
US20020172200
Pub Dt:
11/21/2002
Title:
METHOD AND SYSTEM FOR INTEGRATING PACKET TYPE INFORMATION WITH SYNCHRONIZATION SYMBOLS
13
Patent #:
7113507
Issue Dt:
09/26/2006
Application #:
10053461
Filing Dt:
11/07/2001
Publication #:
US20030227947
Pub Dt:
12/11/2003
Title:
METHOD AND SYSTEM FOR COMMUNICATING CONTROL INFORMATION VIA OUT-OF-BAND SYMBOLS
14
Patent #:
7231009
Issue Dt:
06/12/2007
Application #:
10371220
Filing Dt:
02/19/2003
Publication #:
US20040161067
Pub Dt:
08/19/2004
Title:
DATA SYNCHRONIZATION ACROSS AN ASYNCHRONOUS BOUNDARY USING, FOR EXAMPLE, MULTI-PHASE CLOCKS
15
Patent #:
7831778
Issue Dt:
11/09/2010
Application #:
11690629
Filing Dt:
03/23/2007
Publication #:
US20070233938
Pub Dt:
10/04/2007
Title:
SHARED NONVOLATILE MEMORY ARCHITECTURE
16
Patent #:
7908501
Issue Dt:
03/15/2011
Application #:
11690642
Filing Dt:
03/23/2007
Publication #:
US20080235528
Pub Dt:
09/25/2008
Title:
PROGRESSIVE POWER CONTROL OF A MULTI-PORT MEMORY DEVICE
17
Patent #:
7849339
Issue Dt:
12/07/2010
Application #:
11690659
Filing Dt:
03/23/2007
Publication #:
US20080235526
Pub Dt:
09/25/2008
Title:
POWER-SAVING CLOCKING TECHNIQUE
18
Patent #:
7639561
Issue Dt:
12/29/2009
Application #:
11694813
Filing Dt:
03/30/2007
Publication #:
US20070245094
Pub Dt:
10/18/2007
Title:
MULTI-PORT MEMORY DEVICE HAVING VARIABLE PORT SPEEDS
19
Patent #:
7949863
Issue Dt:
05/24/2011
Application #:
11694819
Filing Dt:
03/30/2007
Publication #:
US20070234021
Pub Dt:
10/04/2007
Title:
INTER-PORT COMMUNICATION IN A MULTI-PORT MEMORY DEVICE
20
Patent #:
7903684
Issue Dt:
03/08/2011
Application #:
11828286
Filing Dt:
07/25/2007
Publication #:
US20080126824
Pub Dt:
05/29/2008
Title:
COMMUNICATIONS ARCHITECTURE FOR TRANSMISSION OF DATA BETWEEN MEMORY BANK CACHES AND PORTS
21
Patent #:
8160192
Issue Dt:
04/17/2012
Application #:
11861175
Filing Dt:
09/25/2007
Publication #:
US20080075222
Pub Dt:
03/27/2008
Title:
SIGNAL INTERLEAVING FOR SERIAL CLOCK AND DATA RECOVERY
22
Patent #:
8001334
Issue Dt:
08/16/2011
Application #:
11952052
Filing Dt:
12/06/2007
Publication #:
US20090150621
Pub Dt:
06/11/2009
Title:
BANK SHARING AND REFRESH IN A SHARED MULTI-PORT MEMORY DEVICE
23
Patent #:
8036248
Issue Dt:
10/11/2011
Application #:
12260970
Filing Dt:
10/29/2008
Publication #:
US20100103929
Pub Dt:
04/29/2010
Title:
METHOD, APPARATUS, AND SYSTEM FOR AUTOMATIC DATA ALIGNER FOR MULTIPLE SERIAL RECEIVERS
24
Patent #:
7777652
Issue Dt:
08/17/2010
Application #:
12260972
Filing Dt:
10/29/2008
Publication #:
US20100102999
Pub Dt:
04/29/2010
Title:
CODING SYSTEM FOR MEMORY SYSTEMS EMPLOYING HIGH-SPEED SERIAL LINKS
25
Patent #:
8386867
Issue Dt:
02/26/2013
Application #:
12497391
Filing Dt:
07/02/2009
Publication #:
US20110004793
Pub Dt:
01/06/2011
Title:
COMPUTER MEMORY TEST STRUCTURE
26
Patent #:
8543873
Issue Dt:
09/24/2013
Application #:
12683365
Filing Dt:
01/06/2010
Publication #:
US20110167308
Pub Dt:
07/07/2011
Title:
MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS
27
Patent #:
8510487
Issue Dt:
08/13/2013
Application #:
12704417
Filing Dt:
02/11/2010
Publication #:
US20110196997
Pub Dt:
08/11/2011
Title:
HYBRID INTERFACE FOR SERIAL AND PARALLEL COMMUNICATION
28
Patent #:
7978099
Issue Dt:
07/12/2011
Application #:
12847416
Filing Dt:
07/30/2010
Publication #:
US20100295711
Pub Dt:
11/25/2010
Title:
17B/20B CODING SYSTEM
29
Patent #:
8760188
Issue Dt:
06/24/2014
Application #:
13174616
Filing Dt:
06/30/2011
Publication #:
US20130002290
Pub Dt:
01/03/2013
Title:
CONFIGURABLE MULTI-DIMENSIONAL DRIVER AND RECEIVER
30
Patent #:
8667354
Issue Dt:
03/04/2014
Application #:
13776508
Filing Dt:
02/25/2013
Publication #:
US20130173974
Pub Dt:
07/04/2013
Title:
COMPUTER MEMORY TEST STRUCTURE
31
Patent #:
8751709
Issue Dt:
06/10/2014
Application #:
13934147
Filing Dt:
07/02/2013
Publication #:
US20130290581
Pub Dt:
10/31/2013
Title:
HYBRID INTERFACE FOR SERIAL AND PARALLEL COMMUNICATION
32
Patent #:
8839058
Issue Dt:
09/16/2014
Application #:
14035795
Filing Dt:
09/24/2013
Publication #:
US20140026006
Pub Dt:
01/23/2014
Title:
MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS
33
Patent #:
8924805
Issue Dt:
12/30/2014
Application #:
14145751
Filing Dt:
12/31/2013
Publication #:
US20140115414
Pub Dt:
04/24/2014
Title:
COMPUTER MEMORY TEST STRUCTURE
34
Patent #:
9281969
Issue Dt:
03/08/2016
Application #:
14300166
Filing Dt:
06/09/2014
Publication #:
US20140286388
Pub Dt:
09/25/2014
Title:
Configurable Multi-Dimensional Driver and Receiver
Assignor
1
JEFFERIES FINANCE LLC
Exec Dt:
10/28/2015
Assignee
1
LATTICE SEMICONDUCTOR CORPORATION
111 SW 5TH AVENUE
7TH FLOOR
PORTLAND, OREGON 97204
Correspondence name and address
MICHAEL GARRABRANTS
2115 O'NEL DRIVE
SAN JOSE, CA 95131

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