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Patent #:
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Issue Dt:
|
05/30/2000
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Application #:
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09019244
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Filing Dt:
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02/05/1998
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Title:
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METHOD AND APPARATUS FOR A N-NARY LOGIC CIRCUIT USING 1 OF N SIGNALS
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Patent #:
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Issue Dt:
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06/28/2005
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Application #:
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09019278
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Filing Dt:
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02/05/1998
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Title:
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METHOD AND APPARATUS FOR A 1 OF N SIGNAL
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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09019355
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Filing Dt:
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02/05/1998
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Title:
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METHOD AND APPARATUS FOR AN N-NARY LOGIC CIRCUIT USING 1 OF 4 SIGNALS
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09073478
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Filing Dt:
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05/06/1998
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Title:
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METHOD AND APPARATUS FOR ROUTING 1 OF N SIGNALS
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09073479
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Filing Dt:
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05/06/1998
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Title:
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METHOD AND APPARATUS FOR ROUTING 1 OF 4 SIGNALS
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09120771
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Filing Dt:
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07/22/1998
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Title:
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A METHOD AND APPARATUS FOR SELECTING AN INTERMEDIATE RESULT FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09120775
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Filing Dt:
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07/22/1998
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Title:
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METHOD AND APPARATUS FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09120776
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Filing Dt:
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07/22/1998
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Title:
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METHOD AND APPARATUS FOR FORMATTING AN INTERMEDIATE RESULT FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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09120814
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Filing Dt:
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07/22/1998
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Title:
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SHIFTING FOR PARALLEL NORMALIZATION AND ROUNDING TECHNIQUE FOR FLOATING POINT ARITHMETIC OPERATIONS
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09122504
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Filing Dt:
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07/24/1998
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Title:
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METHOD AND APPARATUS FOR TW0-STAGE ADDRESS GENERATION
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09123742
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Filing Dt:
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07/28/1998
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Title:
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METHOD AND APPARATUS FOR LOGIC CIRCUIT TRANSITION DETECTION
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09124207
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Filing Dt:
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07/28/1998
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Title:
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METHOD AND APPARATUS FOR LOGIC CIRCUIT SPEED DETECTION
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Patent #:
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Issue Dt:
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05/30/2000
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Application #:
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09150162
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Filing Dt:
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09/09/1998
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Title:
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METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY WORD LINE GENERATION
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Patent #:
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Issue Dt:
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04/04/2000
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Application #:
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09150258
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Filing Dt:
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09/09/1998
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Title:
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METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY OUTPUT INTERFACE
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09150389
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Filing Dt:
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09/09/1998
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Title:
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METHOD AND APPARATUS FOR AN ADDRESS TRIGGERED RAM CIRCUIT
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09150575
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Filing Dt:
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09/10/1998
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Title:
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METHOD AND APPARATUS FOR AN N-NARY HPG GATE
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09150717
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Filing Dt:
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09/10/1998
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Title:
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METHOD AND APPARATUS FOR AN N-NARY SUM/HPG ADDER/SUBTRACTOR GATE
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09150720
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Filing Dt:
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09/10/1998
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Title:
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METHOD AND APPARATUS FOR AN N-NARY SUM/HPG GATE
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09150829
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Filing Dt:
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09/10/1998
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Title:
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METHOD AND APPARATUS FOR AN N-NARY ADDER GATE
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09179330
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Filing Dt:
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10/27/1998
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Title:
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METHOD AND APPARATUS FOR LOGIC SYNCHRONIZATION
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09179626
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Filing Dt:
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10/27/1998
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Title:
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METHOD AND APPARATUS THAT ALLOWS THE LOGIC STATE OF A LOGIC GATE TO BE TESTED WHEN STOPPING OR STARTING THE LOGIC GATE'S CLOCK
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09179745
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Filing Dt:
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10/27/1998
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Title:
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METHOD AND APPARATUS FOR GENERATING CLOCK SIGNALS
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09181405
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Filing Dt:
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10/28/1998
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Title:
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METHOD AND APPARATUS FOR AN ENHANCED FLOATING POINT UNIT WITH GRAPHICS AND INTEGER CAPABILITIES
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09181406
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Filing Dt:
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10/28/1998
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Title:
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METHOD AND APPARATUS FOR A LATE PIPELINE ENHANCED FLOATING POINT UNIT
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09186843
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Filing Dt:
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11/05/1998
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Title:
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1 OF 4 MULTIPLIER
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09191813
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Filing Dt:
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11/13/1998
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Title:
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METHOD AND APPARATUS FOR BUILT-IN SELF-TEST OF LOGIC CIRCUITRY
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09195024
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Filing Dt:
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11/18/1998
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Title:
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METHOD AND APPARATUS FOR SATURATION IN AN N-NARY ADDER/SUBTRACTOR
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09195751
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Filing Dt:
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11/18/1998
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Title:
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METHOD AND APPARATUS FOR INTERRUPTION OF CARRY PROPAGATION ON PARTITION BOUNDARIES
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09195752
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Filing Dt:
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11/18/1998
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Title:
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METHOD AND APPARATUS FOR DYNAMIC PARTITIONABLE SATURATING ADDER/SUBTRACTOR
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Patent #:
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Issue Dt:
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12/25/2001
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Application #:
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09195757
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Filing Dt:
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11/18/1998
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Title:
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METHOD AND APPARATUS FOR HANDLING PARTIAL REGISTER ACCESSES
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09195758
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Filing Dt:
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11/18/1998
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Title:
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METHOD AND APPARATUS THAT ENFORCES A REGIONAL MEMORY MODEL IN HIERARCHICAL MEMORY SYSTEMS
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09195779
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Filing Dt:
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11/18/1998
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Title:
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METHOD AND APPARATUS FOR TLB MEMORY ORDERING
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09206463
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Filing Dt:
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12/07/1998
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Title:
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METHOD AND APPARATUS FOR 3-STAGE 32-BIT ADDER/SUBSTRACTOR
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09206539
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Filing Dt:
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12/07/1998
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Title:
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METHOD AND APPARATUS FOR A 1 OF 4 SHIFTER
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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09206631
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Filing Dt:
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12/07/1998
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Title:
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METHOD AND APPARATUS FOR AN N-NARY EQUALITY COMPARATOR
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09206830
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Filing Dt:
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12/07/1998
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Title:
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METHOD AND APPARATUS FOR N-NARY INCREMENTOR
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09206900
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Filing Dt:
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12/07/1998
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Title:
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METHOD AND APPARATUS FOR TRANSFORMING PSEUDORANDOM BINARY TEST PATTERNS INTO TEST STIMULUS PATTERNS APPROPRIATE FOR CIRCUITS HAVING 1 OF N ENCODED INPUTS
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09206905
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Filing Dt:
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12/07/1998
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Title:
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METHOD AND APPARATUS FOR TRANSFORMING PSEUDORANDOM BINARY PATTERNS INTO TEST STIMULUS PATTERNS APPROPRIATE FOR CIRCUITS HAVING 1 OF N ENCODED INPUTS
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09206906
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Filing Dt:
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12/07/1998
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Title:
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METHOD AND APPARATUS FOR AN N-NARY MAGNITUDE COMPARATOR
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09207806
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Filing Dt:
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12/09/1998
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Title:
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METHOD AND APPARATUS FOR 1 OF 4 REGISTER FILE DESIGN
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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09209207
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Filing Dt:
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12/10/1998
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Title:
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A METHOD AND APPARATUS FOR A LOGIC CIRCUIT WITH CONSTANT POWER CONSUMPTION
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Patent #:
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Issue Dt:
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12/25/2001
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Application #:
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09209935
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Filing Dt:
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12/11/1998
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Title:
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DYNAMIC 3-LEVEL PARTIAL RESULT MERGE ADDER
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09209967
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Filing Dt:
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12/10/1998
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Title:
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METHOD AND APPARATUS FOR A N-NARY LOGIC CIRCUIT USING CAPACITANCE ISOLATION
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02/05/2002
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09210024
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Filing Dt:
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12/11/1998
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Title:
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METHOD AND APPARATUS FOR A LOGIC CIRCUIT DESIGN TOOL
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Patent #:
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Issue Dt:
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09/11/2001
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09210408
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12/11/1998
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Title:
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METHOD AND APPARATUS FOR N-NARY HARDWARE DESCRIPTION LANGUAGE
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04/02/2002
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09210410
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12/11/1998
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Title:
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METHOD AND APPARATUS FOR N-NARY LOGIC CIRCUIT DESIGN TOOL WITH PRECHARGE CIRCUIT EVALUATION
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09/05/2000
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09291659
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04/14/1999
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Title:
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METHOD AND APPARATUS FOR MULTI-BIT REGISTER CELL
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03/19/2002
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09373516
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08/12/1999
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Title:
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METHOD AND APPARATUS THAT SUPPORTS MULTIPLE ASSIGNMENT CODE
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09/24/2002
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09373840
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08/13/1999
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Title:
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SOFTWARE SYSTEM BUILD METHOD AND APPARATUS THAT SUPPORTS MULTIPLE USERS IN A SOFTWARE DEVELOPMENT ENVIRONMENT
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08/20/2002
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09374588
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08/13/1999
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Title:
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METHOD AND APPARATUS FOR OBJECT CACHE REGISTRATION AND MAINTENANCE IN A NETWORKED SOFTWARE DEVELOPMENT ENVIRONMENT
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05/20/2003
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09398618
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09/17/1999
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Title:
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METHOD AND APPARATUS FOR A 5:2 CARRY-SAVE-ADDER (CSA)
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08/05/2003
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09405474
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09/24/1999
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Title:
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MULTIPLE-STATE SIMULATION FOR NON-BINARY LOGIC
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04/18/2006
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09405618
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09/24/1999
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Title:
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SOFTWARE MODELING OF LOGIC SIGNALS CAPABLE OF HOLDING MORE THAN TWO VALUES
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07/15/2003
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09406016
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09/24/1999
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Title:
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METHOD AND APPARATUS THAT REPORTS MULTIPLE STATUS EVENTS WITH A SINGLE MONITOR
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Patent #:
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05/03/2005
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09406017
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09/24/1999
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Title:
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METHOD AND APPARATUS FOR A MONITOR THAT DETECTS AND REPORTS A STATUS EVENT TO A DATABASE
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06/26/2001
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09458763
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12/10/1999
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Title:
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METHOD AND APPARATUS FOR AN N-NARY LOGIC CIRCUIT
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01/30/2001
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09458766
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12/10/1999
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Title:
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METHOD AND APPARATUS FOR A RAM CIRCUIT HAVING N-NARY OUTPUT INTERFACE
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07/02/2002
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09468759
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12/21/1999
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METHOD AND APPARATUS FOR SCAN OF SYNCHRONIZED DYNAMIC LOGIC USING EMBEDDED SCAN GATES
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06/25/2002
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09468760
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12/21/1999
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METHOD AND APPARATUS FOR A SPECIAL STRESS MODE FOR N-NARY LOGIC THAT INITIALIZES THE LOGIC INTO A FUNCTIONALLY ILLEGAL STATE
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08/07/2001
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09468972
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12/21/1999
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DYNAMIC LOGIC SCAN GATE METHOD AND APPARATUS
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09/16/2003
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09496008
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02/01/2000
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METHOD AND APPARATUS FOR PRE-BRANCH INSTRUCTION
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02/19/2002
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09503397
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02/14/2000
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Title:
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Dynamic adjustment of the clock rate in logic circuits
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04/29/2003
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09527653
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03/17/2000
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ROUNDING ANTICIPATOR FOR FLOATING POINT OPERATIONS
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12/24/2002
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09546412
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04/10/2000
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Title:
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LEADING ZERO/ONE ANTICIPATOR FOR FLOATING POINT OPERATIONS
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07/31/2001
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06/05/2000
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05/27/2003
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06/05/2000
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09/03/2002
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09844686
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04/27/2001
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06/06/2002
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METHOD FOR CALCULATING DYNAMIC LOGIC BLOCK PROPAGATION DELAY TARGETS USING TIME BORROWING
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06/01/2004
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07/09/2001
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11/08/2001
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04/27/2004
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09/28/2001
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01/30/2003
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RANDOM NUMBER INDEXING METHOD AND APPARATUS THAT ELIMINATES SOFTWARE CALL SEQUENCE DEPENDENCY
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08/29/2006
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09/28/2001
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04/04/2002
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GRID THAT TRACKS THE OCCURRENCE OF A N-DIMENSIONAL MATRIX OF COMBINATORIAL EVENTS IN A SIMULATION USING A LINEAR INDEX
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05/04/2004
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10155042
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05/24/2002
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11/28/2002
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GENERATION OF ROUTE RULES
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05/24/2005
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10164040
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06/06/2002
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12/26/2002
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REARRANGING DATA BETWEEN VECTOR AND MATRIX FORMS IN A SIMD MATRIX PROCESSOR
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03/18/2008
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06/21/2002
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03/06/2003
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MONITOR MANAGER THAT CREATES AND EXECUTES STATE MACHINE-BASED MONITOR INSTANCES IN A DIGITAL SIMULATION
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03/30/2004
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03/06/2003
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Title:
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STATIC TRANSMISSTION OF FAST14 LOGIC 1-OF-N SIGNALS
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10187879
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Filing Dt:
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07/02/2002
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Publication #:
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Pub Dt:
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06/12/2003
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Title:
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STATIC STORAGE ELEMENT FOR DYNAMIC LOGIC
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Patent #:
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Issue Dt:
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05/30/2006
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10300289
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11/20/2002
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Publication #:
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Pub Dt:
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01/08/2004
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Title:
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NULL VALUE PROPAGATION FOR FAST14 LOGIC
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Patent #:
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Issue Dt:
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05/15/2007
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10738278
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12/16/2003
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Publication #:
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Pub Dt:
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03/17/2005
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Title:
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PHYSICAL REALIZATION OF DYNAMIC LOGIC USING PARAMETERIZED TILE PARTITIONING
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Patent #:
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11/20/2007
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10738281
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12/16/2003
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07/15/2004
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Title:
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EXPANSION SYNTAX
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Patent #:
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06/07/2011
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12526691
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08/11/2009
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Publication #:
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Pub Dt:
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02/25/2010
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Title:
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GENERATING TEST BENCHES FOR PRE-SILICON VALIDATION OF RETIMED COMPLEX IC DESIGNS AGAINST A REFERENCE DESIGN
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Patent #:
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06/07/2011
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12526691
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08/11/2009
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Publication #:
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Pub Dt:
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02/25/2010
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PCT #:
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US0855587
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Title:
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GENERATING TEST BENCHES FOR PRE-SILICON VALIDATION OF RETIMED COMPLEX IC DESIGNS AGAINST A REFERENCE DESIGN
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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12743689
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05/19/2010
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Publication #:
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Pub Dt:
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10/07/2010
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PCT #:
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US0883962
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Title:
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CHARGE RECYCLING A 1 OF N NDL GATE WITH A TIME VARYING POWER SUPPLY
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Patent #:
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Issue Dt:
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05/21/2013
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13127936
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05/05/2011
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PCT #:
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US0949930
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Title:
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Method For Piecewise Hierarchical Sequential Verification
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Patent #:
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05/14/2013
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13128153
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05/06/2011
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PCT #:
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US0962337
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Title:
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METHOD FOR PREPARING RE-ARCHITECTED DESIGNS FOR SEQUENTIAL EQUIVALENCE CHECKING
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