Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 029500/0335 | |
| Pages: | 4 |
| | Recorded: | 12/19/2012 | | |
Attorney Dkt #: | 13335/12045 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13719559
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Filing Dt:
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12/19/2012
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Publication #:
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Pub Dt:
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06/19/2014
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Title:
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Method and Apparatus for Isolating and/or Debugging Defects in Integrated Circuit Designs
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Assignee
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2655 SEELY AVENUE |
BUILDING 5 |
SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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CADENCE DESIGN SYSTEMS, INC.
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C/O KENYON & KENYON LLP
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1801 PAGE MILL ROAD, SUITE 210
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PALO ALTO, CA 94304-1216
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