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|
Patent #:
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|
Issue Dt:
|
08/17/2010
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Application #:
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11612863
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Filing Dt:
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12/19/2006
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Publication #:
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|
Pub Dt:
|
06/19/2008
| | | | |
Title:
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ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
11612874
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Filing Dt:
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12/19/2006
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Publication #:
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|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
PORTABLE DIGITAL RIGHTS MANAGEMENT (DRM)
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Patent #:
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|
Issue Dt:
|
04/06/2010
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Application #:
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11612992
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Filing Dt:
|
12/19/2006
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Publication #:
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|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING
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|
Patent #:
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|
Issue Dt:
|
11/17/2009
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Application #:
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11613379
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Filing Dt:
|
12/20/2006
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Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR ADAPTIVE MEMORY CELL OVERERASE COMPENSATION
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|
Patent #:
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|
Issue Dt:
|
12/01/2009
|
Application #:
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11613383
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Filing Dt:
|
12/20/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
FLASH MEMORY DEVICE WITH EXTERNAL HIGH VOLTAGE SUPPLY
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|
Patent #:
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|
Issue Dt:
|
08/03/2010
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Application #:
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11613513
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Filing Dt:
|
12/20/2006
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Publication #:
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|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION
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Patent #:
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|
Issue Dt:
|
02/14/2012
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Application #:
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11613620
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Filing Dt:
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12/20/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
NEAR FIELD COMMUNICATION, SECURITY AND NON-VOLATILE MEMORY INTEGRATED SUB-SYSTEM FOR EMBEDDED PORTABLE APPLICATIONS
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|
Patent #:
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|
Issue Dt:
|
05/29/2012
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Application #:
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11613627
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Filing Dt:
|
12/20/2006
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Publication #:
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|
Pub Dt:
|
06/26/2008
| | | | |
Title:
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SECURE DATA VERIFICATION VIA BIOMETRIC INPUT
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|
Patent #:
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|
Issue Dt:
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05/29/2012
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Application #:
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11613691
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Filing Dt:
|
12/20/2006
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Publication #:
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|
Pub Dt:
|
05/08/2008
| | | | |
Title:
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MULTIPLE STAKEHOLDER SECURE MEMORY PARTITIONING AND ACCESS CONTROL
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|
Patent #:
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|
Issue Dt:
|
01/06/2009
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Application #:
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11613832
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Filing Dt:
|
12/20/2006
|
Publication #:
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|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS
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|
Patent #:
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|
Issue Dt:
|
02/23/2010
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Application #:
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11614048
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Filing Dt:
|
12/20/2006
|
Publication #:
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|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
METHODS FOR FABRICATING A SPLIT CHARGE STORAGE NODE SEMICONDUCTOR MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
12/22/2009
|
Application #:
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11614050
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Filing Dt:
|
12/20/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
METHODS FOR FABRICATING A MEMORY DEVICE INCLUDING A DUAL BIT MEMORY CELL
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|
|
Patent #:
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|
Issue Dt:
|
05/21/2013
|
Application #:
|
11614053
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Filing Dt:
|
12/20/2006
|
Publication #:
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|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING
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|
|
Patent #:
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|
Issue Dt:
|
05/29/2012
|
Application #:
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11614257
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Filing Dt:
|
12/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
NON-VOLATILE MEMORY SUB-SYSTEM INTEGRATED WITH SECURITY FOR STORING NEAR FIELD TRANSACTIONS
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|
Patent #:
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|
Issue Dt:
|
09/04/2012
|
Application #:
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11614306
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Filing Dt:
|
12/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
SOLID-STATE MEMORY-BASED GENERATION AND HANDLING OF SECURITY AUTHENTICATION TOKENS
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|
|
Patent #:
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|
Issue Dt:
|
01/15/2013
|
Application #:
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11614309
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Filing Dt:
|
12/21/2006
|
Publication #:
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|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
SECURE CO-PROCESSING MEMORY CONTROLLER INTEGRATED INTO AN EMBEDDED MEMORY SUBSYSTEM
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|
|
Patent #:
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|
Issue Dt:
|
06/29/2010
|
Application #:
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11614767
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Filing Dt:
|
12/21/2006
|
Publication #:
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|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
FLOATING GATE PROCESS METHODOLOGY
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|
|
Patent #:
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|
Issue Dt:
|
04/06/2010
|
Application #:
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11614770
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Filing Dt:
|
12/21/2006
|
Publication #:
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|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
COPPER PROCESS METHODOLOGY
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|
|
Patent #:
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|
Issue Dt:
|
01/04/2011
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Application #:
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11614801
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Filing Dt:
|
12/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
ZERO INTERFACE POLYSILICON TO POLYSILICON GATE FOR FLASH MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
07/22/2014
|
Application #:
|
11614815
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Filing Dt:
|
12/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
MEMORY SYSTEM WITH FIN FET TECHNOLOGY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11614839
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Filing Dt:
|
12/21/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
MEMORY SYSTEM WITH SELECT GATE ERASE
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|
|
Patent #:
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|
Issue Dt:
|
12/09/2008
|
Application #:
|
11615280
|
Filing Dt:
|
12/22/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
NEGATIVE WORDLINE BIAS FOR REDUCTION OF LEAKAGE CURRENT DURING FLASH MEMORY OPERATION
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|
|
Patent #:
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|
Issue Dt:
|
03/30/2010
|
Application #:
|
11615365
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Filing Dt:
|
12/22/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11615425
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Filing Dt:
|
12/22/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
|
|
|
Patent #:
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|
Issue Dt:
|
07/16/2013
|
Application #:
|
11615489
|
Filing Dt:
|
12/22/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
|
|
|
Patent #:
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|
Issue Dt:
|
02/01/2011
|
Application #:
|
11615492
|
Filing Dt:
|
12/22/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
SYSTEMS AND METHODS FOR DISTINGUISHING BETWEEN ACTUAL DATA AND ERASED/BLANK MEMORY WITH REGARD TO ENCRYPTED DATA
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|
|
Patent #:
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|
Issue Dt:
|
11/24/2009
|
Application #:
|
11615563
|
Filing Dt:
|
12/22/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
MEMORY DEVICE HAVING IMPLANTED OXIDE TO BLOCK ELECTRON DRIFT, AND METHOD OF MANUFACTURING THE SAME
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|
|
Patent #:
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|
Issue Dt:
|
02/07/2012
|
Application #:
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11615583
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Filing Dt:
|
12/22/2006
|
Publication #:
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|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT WAFER SYSTEM WITH CONTROL STRATEGY
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|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11615710
|
Filing Dt:
|
12/22/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
REPETITIVE ERASE VERIFY TECHNIQUE FOR FLASH MEMORY DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
06/23/2009
|
Application #:
|
11616045
|
Filing Dt:
|
12/26/2006
|
Publication #:
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|
Pub Dt:
|
05/10/2007
| | | | |
Title:
|
SWITCHABLE MEMORY DIODE - A NEW MEMORY DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
03/02/2010
|
Application #:
|
11616085
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Filing Dt:
|
12/26/2006
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
MEMORY DEVICE ETCH METHODS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11616385
|
Filing Dt:
|
12/27/2006
|
Publication #:
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|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
PERSONAL DIGITAL RIGHTS MANAGEMENT AGENT-SERVER
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|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
11616544
|
Filing Dt:
|
12/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
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|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
11616563
|
Filing Dt:
|
12/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
METHOD FOR IMPROVED PLANARIZATION IN SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
12/13/2011
|
Application #:
|
11616718
|
Filing Dt:
|
12/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
DUAL-BIT MEMORY DEVICE HAVING ISOLATION MATERIAL DISPOSED UNDERNEATH A BIT LINE SHARED BY ADJACENT DUAL-BIT MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11618075
|
Filing Dt:
|
12/29/2006
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
SYSTEMS AND METHODS FOR ACCESS VIOLATION MANAGEMENT OF SECURED MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
11625150
|
Filing Dt:
|
01/19/2007
|
Publication #:
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|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
FULLY ASSOCIATIVE BANKING FOR MEMORY
|
|
|
Patent #:
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|
Issue Dt:
|
08/07/2012
|
Application #:
|
11625158
|
Filing Dt:
|
01/19/2007
|
Publication #:
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|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
BYTE MASK COMMAND FOR MEMORIES
|
|
|
Patent #:
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|
Issue Dt:
|
04/08/2008
|
Application #:
|
11633791
|
Filing Dt:
|
12/05/2006
|
Title:
|
METHOD OF PROGRAMMING, ERASING AND READING MEMORY CELLS IN A RESISTIVE MEMORY ARRAY
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|
|
Patent #:
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|
Issue Dt:
|
02/22/2011
|
Application #:
|
11633800
|
Filing Dt:
|
12/05/2006
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
METHODS OF PROGRAMMING AND ERASING RESISTIVE MEMORY DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
11633844
|
Filing Dt:
|
12/05/2006
|
Publication #:
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|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
GETTERING/STOP LAYER FOR PREVENTION OF REDUCTION OF INSULATING OXIDE IN METAL-INSULATOR-METAL DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
|
11633845
|
Filing Dt:
|
12/05/2006
|
Publication #:
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|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
METHOD OF PROGRAMMING MEMORY DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
01/03/2012
|
Application #:
|
11633929
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Filing Dt:
|
12/05/2006
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
DAMASCENE METAL-INSULATOR-METAL (MIM) DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11633930
|
Filing Dt:
|
12/05/2006
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
TEST STRUCTURES FOR DEVELOPMENT OF METAL-INSULATOR-METAL (MIM) DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
12/13/2011
|
Application #:
|
11633940
|
Filing Dt:
|
12/05/2006
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
METHOD OF PROGRAMMING, ERASING AND REPAIRING A MEMORY DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
03/29/2011
|
Application #:
|
11633941
|
Filing Dt:
|
12/05/2006
|
Publication #:
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|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
METHOD OF ERASING A RESISTIVE MEMORY DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11633942
|
Filing Dt:
|
12/05/2006
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
METHOD OF FABRICATING METAL-INSULATOR-METAL (MIM) DEVICE WITH STABLE DATA RETENTION
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|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
11634776
|
Filing Dt:
|
12/06/2006
|
Publication #:
|
|
Pub Dt:
|
06/12/2008
| | | | |
Title:
|
METHOD TO PROVIDE A HIGHER REFERENCE VOLTAGE AT A LOWER POWER SUPPLY IN FLASH MEMORY DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
10/27/2015
|
Application #:
|
11634777
|
Filing Dt:
|
12/06/2006
|
Publication #:
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|
Pub Dt:
|
06/12/2008
| | | | |
Title:
|
Barrier region underlying source/drain regions for dual-bit memory devices
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|
|
Patent #:
|
|
Issue Dt:
|
03/15/2011
|
Application #:
|
11636064
|
Filing Dt:
|
12/06/2006
|
Publication #:
|
|
Pub Dt:
|
06/21/2007
| | | | |
Title:
|
SEMICONDUCTOR MANUFACTURING APPARATUS AND CONTROL SYSTEM AND CONTROL METHOD THEREFOR
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|
|
Patent #:
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|
Issue Dt:
|
11/11/2008
|
Application #:
|
11636111
|
Filing Dt:
|
12/07/2006
|
Publication #:
|
|
Pub Dt:
|
08/02/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR
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|
|
Patent #:
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|
Issue Dt:
|
10/20/2009
|
Application #:
|
11636155
|
Filing Dt:
|
12/07/2006
|
Publication #:
|
|
Pub Dt:
|
06/28/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11637260
|
Filing Dt:
|
12/11/2006
|
Publication #:
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|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
|
|
|
Patent #:
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|
Issue Dt:
|
05/13/2008
|
Application #:
|
11639128
|
Filing Dt:
|
12/13/2006
|
Publication #:
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|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
CONTROLLING A NONVOLATILE STORAGE DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
10/13/2015
|
Application #:
|
11639666
|
Filing Dt:
|
12/15/2006
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
METHOD FOR FABRICATING MEMORY CELLS HAVING SPLIT CHARGE STORAGE NODES
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|
|
Patent #:
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|
Issue Dt:
|
06/29/2010
|
Application #:
|
11639935
|
Filing Dt:
|
12/15/2006
|
Publication #:
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|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
METHODS AND SYSTEMS FOR MEMORY DEVICES
|
|
|
Patent #:
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|
Issue Dt:
|
12/02/2008
|
Application #:
|
11639936
|
Filing Dt:
|
12/15/2006
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
DRAIN VOLTAGE REGULATOR
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11641506
|
Filing Dt:
|
12/19/2006
|
Publication #:
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|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
Stress management in BGA packaging
|
|
|
Patent #:
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|
Issue Dt:
|
08/02/2011
|
Application #:
|
11641646
|
Filing Dt:
|
12/19/2006
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
RESISTIVE MEMORY ARRAY USING P-I-N DIODE SELECT DEVICE AND METHODS OF FABRICATION THEREOF
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|
|
Patent #:
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|
Issue Dt:
|
07/29/2014
|
Application #:
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11641647
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Filing Dt:
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12/19/2006
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Publication #:
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Pub Dt:
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06/19/2008
| | | | |
Title:
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Method of depositing copper using physical vapor deposition
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Patent #:
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Issue Dt:
|
01/05/2010
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Application #:
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11642412
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Filing Dt:
|
12/19/2006
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Title:
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SYSTEM AND METHOD FOR MAINTAINING RAM COMMAND TIMING ACROSS PHASE-SHIFTED TIME DOMAINS
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Patent #:
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Issue Dt:
|
11/11/2008
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Application #:
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11642477
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Filing Dt:
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12/20/2006
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Publication #:
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Pub Dt:
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06/26/2008
| | | | |
Title:
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MEMORY DEVICE WITH ACTIVE LAYER OF DENDRIMERIC MATERIAL
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Patent #:
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Issue Dt:
|
07/21/2009
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Application #:
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11644031
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Filing Dt:
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12/22/2006
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Publication #:
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Pub Dt:
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06/26/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
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Patent #:
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Issue Dt:
|
08/11/2009
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Application #:
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11644161
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Filing Dt:
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12/22/2006
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Publication #:
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Pub Dt:
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06/26/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
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Patent #:
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Issue Dt:
|
07/12/2011
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Application #:
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11645475
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Filing Dt:
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12/26/2006
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Publication #:
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Pub Dt:
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06/26/2008
| | | | |
Title:
|
THIN OXIDE DUMMY TILING AS CHARGE PROTECTION
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Patent #:
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Issue Dt:
|
03/02/2010
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Application #:
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11646157
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Filing Dt:
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12/26/2006
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Publication #:
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Pub Dt:
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06/26/2008
| | | | |
Title:
|
DEEP BITLINE IMPLANT TO AVOID PROGRAM DISTURB
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11650907
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Filing Dt:
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01/08/2007
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Publication #:
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Pub Dt:
|
01/01/2009
| | | | |
Title:
|
Structure and method for wire bond integrity check on BGA substrates using indirect electrical interconnectivity pathway between wire bonds and ground
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Patent #:
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Issue Dt:
|
09/28/2010
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Application #:
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11653649
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Filing Dt:
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01/12/2007
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Publication #:
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Pub Dt:
|
07/17/2008
| | | | |
Title:
|
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
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|
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Patent #:
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Issue Dt:
|
10/16/2007
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Application #:
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11653655
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Filing Dt:
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01/16/2007
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Publication #:
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Pub Dt:
|
05/24/2007
| | | | |
Title:
|
METHODS AND SYSTEMS FOR HIGH WRITE PERFORMANCE IN MULTI-BIT FLASH MEMORY DEVICES
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|
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Patent #:
|
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Issue Dt:
|
07/28/2009
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Application #:
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11654703
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Filing Dt:
|
01/17/2007
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Publication #:
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Pub Dt:
|
07/17/2008
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD
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|
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Patent #:
|
|
Issue Dt:
|
06/28/2011
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Application #:
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11654704
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Filing Dt:
|
01/17/2007
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Publication #:
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Pub Dt:
|
07/17/2008
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
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|
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Patent #:
|
|
Issue Dt:
|
07/20/2010
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Application #:
|
11656437
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Filing Dt:
|
01/23/2007
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Publication #:
|
|
Pub Dt:
|
05/24/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
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Application #:
|
11656438
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Filing Dt:
|
01/23/2007
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Publication #:
|
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Pub Dt:
|
05/24/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
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Application #:
|
11687436
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Filing Dt:
|
03/16/2007
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Publication #:
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|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
DIVISION-BASED SENSING AND PARTITIONING OF ELECTRONIC MEMORY
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|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11687479
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Filing Dt:
|
03/16/2007
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Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
MEMORY STORAGE VIA AN INTERNAL COMPRESSION ALGORITHM
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|
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Patent #:
|
|
Issue Dt:
|
09/21/2010
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Application #:
|
11687487
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Filing Dt:
|
03/16/2007
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Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
STATE CHANGE SENSING
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|
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Patent #:
|
|
Issue Dt:
|
11/16/2010
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Application #:
|
11687492
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Filing Dt:
|
03/16/2007
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Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
HIGH ACCURACY ADAPTIVE PROGRAMMING
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11694089
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Filing Dt:
|
03/30/2007
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Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
MEMORY SYSTEM WITH DEPLETION GATE
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|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
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Application #:
|
11702845
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Filing Dt:
|
02/05/2007
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Publication #:
|
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Pub Dt:
|
09/06/2007
| | | | |
Title:
|
DUAL STORAGE NODE MEMORY
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|
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Patent #:
|
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Issue Dt:
|
06/03/2014
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Application #:
|
11702846
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Filing Dt:
|
02/05/2007
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Publication #:
|
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Pub Dt:
|
09/06/2007
| | | | |
Title:
|
FLASH MEMORY CELLS HAVING TRENCHED STORAGE ELEMENTS
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|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11702847
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Filing Dt:
|
02/05/2007
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Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
Dual charge storage node with undercut gate oxide for deep sub-micron memory cell
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|
|
Patent #:
|
|
Issue Dt:
|
03/27/2012
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Application #:
|
11712299
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Filing Dt:
|
02/27/2007
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Publication #:
|
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Pub Dt:
|
09/13/2007
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING LOWER LEAKAGE CURRENT BETWEEN SEMICONDUCTOR SUBSTRATE AND BIT LINES
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|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
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Application #:
|
11724711
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Filing Dt:
|
03/16/2007
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Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
CYCLING IMPROVEMENT USING HIGHER ERASE BIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2016
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Application #:
|
11724725
|
Filing Dt:
|
03/16/2007
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Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
Dielectric extension to mitigate short channel effects
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
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Application #:
|
11724726
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Filing Dt:
|
03/16/2007
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
USING IMPLANTED POLY-1 TO IMPROVE CHARGING PROTECTION IN DUAL-POLY PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
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Application #:
|
11724773
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Filing Dt:
|
03/16/2007
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
MULTI-STATE RESISTANCE CHANGING MEMORY WITH A WORD LINE DRIVER FOR APPLYING A SAME PROGRAM VOLTAGE TO THE WORD LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11724774
|
Filing Dt:
|
03/16/2007
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
METHODS AND SYSTEMS FOR RECOVERING DATA IN A NONVOLATILE MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
11724775
|
Filing Dt:
|
03/16/2007
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
USING THICK SPACER FOR BITLINE IMPLANT THEN REMOVE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
11724788
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Filing Dt:
|
03/16/2007
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Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
NON-VOLATILE RESISTANCE CHANGING FOR ADVANCED MEMORY APPLICATIONS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11735229
|
Filing Dt:
|
04/13/2007
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11735241
|
Filing Dt:
|
04/13/2007
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
MEMORY SYSTEM WITH POLY METAL GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
11741996
|
Filing Dt:
|
04/30/2007
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
11741998
|
Filing Dt:
|
04/30/2007
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
METHOD TO OBTAIN MULTIPLE GATE THICKNESSES USING IN-SITU GATE ETCH MASK APPROACH
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
11742003
|
Filing Dt:
|
04/30/2007
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
TRIPLE POLY-SI REPLACEMENT SCHEME FOR MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11742371
|
Filing Dt:
|
04/30/2007
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
ADAPTIVE DETECTION OF THRESHOLD LEVELS IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11745327
|
Filing Dt:
|
05/07/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
11746122
|
Filing Dt:
|
05/09/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
11747608
|
Filing Dt:
|
05/11/2007
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
MANAGING FLASH MEMORY BASED UPON USAGE HISTORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11748215
|
Filing Dt:
|
05/14/2007
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
VARIABLE SALICIDE BLOCK FOR RESISTANCE EQUALIZATION IN AN ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
11748743
|
Filing Dt:
|
05/15/2007
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
METHODS OF FORMING SILICIDES OF DIFFERENT THICKNESSES ON DIFFERENT STRUCTURES
|
|