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Reel/Frame:024522/0338   Pages: 225
Recorded: 06/04/2010
Attorney Dkt #:042243-0080
Conveyance: SECURITY AGREEMENT
Total properties: 1906
Page 16 of 20
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
Patent #:
Issue Dt:
08/17/2010
Application #:
11612863
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
06/19/2008
Title:
ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS
2
Patent #:
NONE
Issue Dt:
Application #:
11612874
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
06/19/2008
Title:
PORTABLE DIGITAL RIGHTS MANAGEMENT (DRM)
3
Patent #:
Issue Dt:
04/06/2010
Application #:
11612992
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
06/19/2008
Title:
METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING
4
Patent #:
Issue Dt:
11/17/2009
Application #:
11613379
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
METHOD AND APPARATUS FOR ADAPTIVE MEMORY CELL OVERERASE COMPENSATION
5
Patent #:
Issue Dt:
12/01/2009
Application #:
11613383
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
FLASH MEMORY DEVICE WITH EXTERNAL HIGH VOLTAGE SUPPLY
6
Patent #:
Issue Dt:
08/03/2010
Application #:
11613513
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION
7
Patent #:
Issue Dt:
02/14/2012
Application #:
11613620
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
NEAR FIELD COMMUNICATION, SECURITY AND NON-VOLATILE MEMORY INTEGRATED SUB-SYSTEM FOR EMBEDDED PORTABLE APPLICATIONS
8
Patent #:
Issue Dt:
05/29/2012
Application #:
11613627
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
SECURE DATA VERIFICATION VIA BIOMETRIC INPUT
9
Patent #:
Issue Dt:
05/29/2012
Application #:
11613691
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
05/08/2008
Title:
MULTIPLE STAKEHOLDER SECURE MEMORY PARTITIONING AND ACCESS CONTROL
10
Patent #:
Issue Dt:
01/06/2009
Application #:
11613832
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS
11
Patent #:
Issue Dt:
02/23/2010
Application #:
11614048
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
METHODS FOR FABRICATING A SPLIT CHARGE STORAGE NODE SEMICONDUCTOR MEMORY
12
Patent #:
Issue Dt:
12/22/2009
Application #:
11614050
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
METHODS FOR FABRICATING A MEMORY DEVICE INCLUDING A DUAL BIT MEMORY CELL
13
Patent #:
Issue Dt:
05/21/2013
Application #:
11614053
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING
14
Patent #:
Issue Dt:
05/29/2012
Application #:
11614257
Filing Dt:
12/21/2006
Publication #:
Pub Dt:
06/26/2008
Title:
NON-VOLATILE MEMORY SUB-SYSTEM INTEGRATED WITH SECURITY FOR STORING NEAR FIELD TRANSACTIONS
15
Patent #:
Issue Dt:
09/04/2012
Application #:
11614306
Filing Dt:
12/21/2006
Publication #:
Pub Dt:
06/26/2008
Title:
SOLID-STATE MEMORY-BASED GENERATION AND HANDLING OF SECURITY AUTHENTICATION TOKENS
16
Patent #:
Issue Dt:
01/15/2013
Application #:
11614309
Filing Dt:
12/21/2006
Publication #:
Pub Dt:
05/08/2008
Title:
SECURE CO-PROCESSING MEMORY CONTROLLER INTEGRATED INTO AN EMBEDDED MEMORY SUBSYSTEM
17
Patent #:
Issue Dt:
06/29/2010
Application #:
11614767
Filing Dt:
12/21/2006
Publication #:
Pub Dt:
06/26/2008
Title:
FLOATING GATE PROCESS METHODOLOGY
18
Patent #:
Issue Dt:
04/06/2010
Application #:
11614770
Filing Dt:
12/21/2006
Publication #:
Pub Dt:
06/26/2008
Title:
COPPER PROCESS METHODOLOGY
19
Patent #:
Issue Dt:
01/04/2011
Application #:
11614801
Filing Dt:
12/21/2006
Publication #:
Pub Dt:
06/26/2008
Title:
ZERO INTERFACE POLYSILICON TO POLYSILICON GATE FOR FLASH MEMORY
20
Patent #:
Issue Dt:
07/22/2014
Application #:
11614815
Filing Dt:
12/21/2006
Publication #:
Pub Dt:
06/26/2008
Title:
MEMORY SYSTEM WITH FIN FET TECHNOLOGY
21
Patent #:
NONE
Issue Dt:
Application #:
11614839
Filing Dt:
12/21/2006
Publication #:
Pub Dt:
06/26/2008
Title:
MEMORY SYSTEM WITH SELECT GATE ERASE
22
Patent #:
Issue Dt:
12/09/2008
Application #:
11615280
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
NEGATIVE WORDLINE BIAS FOR REDUCTION OF LEAKAGE CURRENT DURING FLASH MEMORY OPERATION
23
Patent #:
Issue Dt:
03/30/2010
Application #:
11615365
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS
24
Patent #:
NONE
Issue Dt:
Application #:
11615425
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
25
Patent #:
Issue Dt:
07/16/2013
Application #:
11615489
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
26
Patent #:
Issue Dt:
02/01/2011
Application #:
11615492
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
SYSTEMS AND METHODS FOR DISTINGUISHING BETWEEN ACTUAL DATA AND ERASED/BLANK MEMORY WITH REGARD TO ENCRYPTED DATA
27
Patent #:
Issue Dt:
11/24/2009
Application #:
11615563
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
MEMORY DEVICE HAVING IMPLANTED OXIDE TO BLOCK ELECTRON DRIFT, AND METHOD OF MANUFACTURING THE SAME
28
Patent #:
Issue Dt:
02/07/2012
Application #:
11615583
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
INTEGRATED CIRCUIT WAFER SYSTEM WITH CONTROL STRATEGY
29
Patent #:
Issue Dt:
06/10/2008
Application #:
11615710
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
REPETITIVE ERASE VERIFY TECHNIQUE FOR FLASH MEMORY DEVICES
30
Patent #:
Issue Dt:
06/23/2009
Application #:
11616045
Filing Dt:
12/26/2006
Publication #:
Pub Dt:
05/10/2007
Title:
SWITCHABLE MEMORY DIODE - A NEW MEMORY DEVICE
31
Patent #:
Issue Dt:
03/02/2010
Application #:
11616085
Filing Dt:
12/26/2006
Publication #:
Pub Dt:
06/26/2008
Title:
MEMORY DEVICE ETCH METHODS
32
Patent #:
NONE
Issue Dt:
Application #:
11616385
Filing Dt:
12/27/2006
Publication #:
Pub Dt:
07/03/2008
Title:
PERSONAL DIGITAL RIGHTS MANAGEMENT AGENT-SERVER
33
Patent #:
Issue Dt:
02/01/2011
Application #:
11616544
Filing Dt:
12/27/2006
Publication #:
Pub Dt:
07/03/2008
Title:
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
34
Patent #:
Issue Dt:
04/13/2010
Application #:
11616563
Filing Dt:
12/27/2006
Publication #:
Pub Dt:
07/03/2008
Title:
METHOD FOR IMPROVED PLANARIZATION IN SEMICONDUCTOR DEVICES
35
Patent #:
Issue Dt:
12/13/2011
Application #:
11616718
Filing Dt:
12/27/2006
Publication #:
Pub Dt:
07/03/2008
Title:
DUAL-BIT MEMORY DEVICE HAVING ISOLATION MATERIAL DISPOSED UNDERNEATH A BIT LINE SHARED BY ADJACENT DUAL-BIT MEMORY CELLS
36
Patent #:
Issue Dt:
11/16/2010
Application #:
11618075
Filing Dt:
12/29/2006
Publication #:
Pub Dt:
07/03/2008
Title:
SYSTEMS AND METHODS FOR ACCESS VIOLATION MANAGEMENT OF SECURED MEMORY
37
Patent #:
Issue Dt:
07/24/2012
Application #:
11625150
Filing Dt:
01/19/2007
Publication #:
Pub Dt:
07/24/2008
Title:
FULLY ASSOCIATIVE BANKING FOR MEMORY
38
Patent #:
Issue Dt:
08/07/2012
Application #:
11625158
Filing Dt:
01/19/2007
Publication #:
Pub Dt:
07/24/2008
Title:
BYTE MASK COMMAND FOR MEMORIES
39
Patent #:
Issue Dt:
04/08/2008
Application #:
11633791
Filing Dt:
12/05/2006
Title:
METHOD OF PROGRAMMING, ERASING AND READING MEMORY CELLS IN A RESISTIVE MEMORY ARRAY
40
Patent #:
Issue Dt:
02/22/2011
Application #:
11633800
Filing Dt:
12/05/2006
Publication #:
Pub Dt:
06/05/2008
Title:
METHODS OF PROGRAMMING AND ERASING RESISTIVE MEMORY DEVICES
41
Patent #:
Issue Dt:
01/10/2012
Application #:
11633844
Filing Dt:
12/05/2006
Publication #:
Pub Dt:
06/05/2008
Title:
GETTERING/STOP LAYER FOR PREVENTION OF REDUCTION OF INSULATING OXIDE IN METAL-INSULATOR-METAL DEVICE
42
Patent #:
Issue Dt:
07/21/2009
Application #:
11633845
Filing Dt:
12/05/2006
Publication #:
Pub Dt:
06/05/2008
Title:
METHOD OF PROGRAMMING MEMORY DEVICE
43
Patent #:
Issue Dt:
01/03/2012
Application #:
11633929
Filing Dt:
12/05/2006
Publication #:
Pub Dt:
06/05/2008
Title:
DAMASCENE METAL-INSULATOR-METAL (MIM) DEVICE
44
Patent #:
Issue Dt:
12/23/2008
Application #:
11633930
Filing Dt:
12/05/2006
Publication #:
Pub Dt:
06/05/2008
Title:
TEST STRUCTURES FOR DEVELOPMENT OF METAL-INSULATOR-METAL (MIM) DEVICES
45
Patent #:
Issue Dt:
12/13/2011
Application #:
11633940
Filing Dt:
12/05/2006
Publication #:
Pub Dt:
06/05/2008
Title:
METHOD OF PROGRAMMING, ERASING AND REPAIRING A MEMORY DEVICE
46
Patent #:
Issue Dt:
03/29/2011
Application #:
11633941
Filing Dt:
12/05/2006
Publication #:
Pub Dt:
06/05/2008
Title:
METHOD OF ERASING A RESISTIVE MEMORY DEVICE
47
Patent #:
Issue Dt:
06/10/2008
Application #:
11633942
Filing Dt:
12/05/2006
Publication #:
Pub Dt:
06/05/2008
Title:
METHOD OF FABRICATING METAL-INSULATOR-METAL (MIM) DEVICE WITH STABLE DATA RETENTION
48
Patent #:
Issue Dt:
05/25/2010
Application #:
11634776
Filing Dt:
12/06/2006
Publication #:
Pub Dt:
06/12/2008
Title:
METHOD TO PROVIDE A HIGHER REFERENCE VOLTAGE AT A LOWER POWER SUPPLY IN FLASH MEMORY DEVICES
49
Patent #:
Issue Dt:
10/27/2015
Application #:
11634777
Filing Dt:
12/06/2006
Publication #:
Pub Dt:
06/12/2008
Title:
Barrier region underlying source/drain regions for dual-bit memory devices
50
Patent #:
Issue Dt:
03/15/2011
Application #:
11636064
Filing Dt:
12/06/2006
Publication #:
Pub Dt:
06/21/2007
Title:
SEMICONDUCTOR MANUFACTURING APPARATUS AND CONTROL SYSTEM AND CONTROL METHOD THEREFOR
51
Patent #:
Issue Dt:
11/11/2008
Application #:
11636111
Filing Dt:
12/07/2006
Publication #:
Pub Dt:
08/02/2007
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR
52
Patent #:
Issue Dt:
10/20/2009
Application #:
11636155
Filing Dt:
12/07/2006
Publication #:
Pub Dt:
06/28/2007
Title:
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
53
Patent #:
Issue Dt:
12/23/2008
Application #:
11637260
Filing Dt:
12/11/2006
Publication #:
Pub Dt:
08/09/2007
Title:
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
54
Patent #:
Issue Dt:
05/13/2008
Application #:
11639128
Filing Dt:
12/13/2006
Publication #:
Pub Dt:
08/09/2007
Title:
CONTROLLING A NONVOLATILE STORAGE DEVICE
55
Patent #:
Issue Dt:
10/13/2015
Application #:
11639666
Filing Dt:
12/15/2006
Publication #:
Pub Dt:
06/19/2008
Title:
METHOD FOR FABRICATING MEMORY CELLS HAVING SPLIT CHARGE STORAGE NODES
56
Patent #:
Issue Dt:
06/29/2010
Application #:
11639935
Filing Dt:
12/15/2006
Publication #:
Pub Dt:
06/19/2008
Title:
METHODS AND SYSTEMS FOR MEMORY DEVICES
57
Patent #:
Issue Dt:
12/02/2008
Application #:
11639936
Filing Dt:
12/15/2006
Publication #:
Pub Dt:
06/19/2008
Title:
DRAIN VOLTAGE REGULATOR
58
Patent #:
NONE
Issue Dt:
Application #:
11641506
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
06/19/2008
Title:
Stress management in BGA packaging
59
Patent #:
Issue Dt:
08/02/2011
Application #:
11641646
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
06/19/2008
Title:
RESISTIVE MEMORY ARRAY USING P-I-N DIODE SELECT DEVICE AND METHODS OF FABRICATION THEREOF
60
Patent #:
Issue Dt:
07/29/2014
Application #:
11641647
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
06/19/2008
Title:
Method of depositing copper using physical vapor deposition
61
Patent #:
Issue Dt:
01/05/2010
Application #:
11642412
Filing Dt:
12/19/2006
Title:
SYSTEM AND METHOD FOR MAINTAINING RAM COMMAND TIMING ACROSS PHASE-SHIFTED TIME DOMAINS
62
Patent #:
Issue Dt:
11/11/2008
Application #:
11642477
Filing Dt:
12/20/2006
Publication #:
Pub Dt:
06/26/2008
Title:
MEMORY DEVICE WITH ACTIVE LAYER OF DENDRIMERIC MATERIAL
63
Patent #:
Issue Dt:
07/21/2009
Application #:
11644031
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
64
Patent #:
Issue Dt:
08/11/2009
Application #:
11644161
Filing Dt:
12/22/2006
Publication #:
Pub Dt:
06/26/2008
Title:
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
65
Patent #:
Issue Dt:
07/12/2011
Application #:
11645475
Filing Dt:
12/26/2006
Publication #:
Pub Dt:
06/26/2008
Title:
THIN OXIDE DUMMY TILING AS CHARGE PROTECTION
66
Patent #:
Issue Dt:
03/02/2010
Application #:
11646157
Filing Dt:
12/26/2006
Publication #:
Pub Dt:
06/26/2008
Title:
DEEP BITLINE IMPLANT TO AVOID PROGRAM DISTURB
67
Patent #:
NONE
Issue Dt:
Application #:
11650907
Filing Dt:
01/08/2007
Publication #:
Pub Dt:
01/01/2009
Title:
Structure and method for wire bond integrity check on BGA substrates using indirect electrical interconnectivity pathway between wire bonds and ground
68
Patent #:
Issue Dt:
09/28/2010
Application #:
11653649
Filing Dt:
01/12/2007
Publication #:
Pub Dt:
07/17/2008
Title:
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
69
Patent #:
Issue Dt:
10/16/2007
Application #:
11653655
Filing Dt:
01/16/2007
Publication #:
Pub Dt:
05/24/2007
Title:
METHODS AND SYSTEMS FOR HIGH WRITE PERFORMANCE IN MULTI-BIT FLASH MEMORY DEVICES
70
Patent #:
Issue Dt:
07/28/2009
Application #:
11654703
Filing Dt:
01/17/2007
Publication #:
Pub Dt:
07/17/2008
Title:
SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD
71
Patent #:
Issue Dt:
06/28/2011
Application #:
11654704
Filing Dt:
01/17/2007
Publication #:
Pub Dt:
07/17/2008
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
72
Patent #:
Issue Dt:
07/20/2010
Application #:
11656437
Filing Dt:
01/23/2007
Publication #:
Pub Dt:
05/24/2007
Title:
SEMICONDUCTOR MEMORY DEVICE
73
Patent #:
Issue Dt:
01/27/2009
Application #:
11656438
Filing Dt:
01/23/2007
Publication #:
Pub Dt:
05/24/2007
Title:
SEMICONDUCTOR MEMORY DEVICE
74
Patent #:
Issue Dt:
12/14/2010
Application #:
11687436
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
09/18/2008
Title:
DIVISION-BASED SENSING AND PARTITIONING OF ELECTRONIC MEMORY
75
Patent #:
NONE
Issue Dt:
Application #:
11687479
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
09/18/2008
Title:
MEMORY STORAGE VIA AN INTERNAL COMPRESSION ALGORITHM
76
Patent #:
Issue Dt:
09/21/2010
Application #:
11687487
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
09/18/2008
Title:
STATE CHANGE SENSING
77
Patent #:
Issue Dt:
11/16/2010
Application #:
11687492
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
09/18/2008
Title:
HIGH ACCURACY ADAPTIVE PROGRAMMING
78
Patent #:
NONE
Issue Dt:
Application #:
11694089
Filing Dt:
03/30/2007
Publication #:
Pub Dt:
06/26/2008
Title:
MEMORY SYSTEM WITH DEPLETION GATE
79
Patent #:
Issue Dt:
10/22/2013
Application #:
11702845
Filing Dt:
02/05/2007
Publication #:
Pub Dt:
09/06/2007
Title:
DUAL STORAGE NODE MEMORY
80
Patent #:
Issue Dt:
06/03/2014
Application #:
11702846
Filing Dt:
02/05/2007
Publication #:
Pub Dt:
09/06/2007
Title:
FLASH MEMORY CELLS HAVING TRENCHED STORAGE ELEMENTS
81
Patent #:
NONE
Issue Dt:
Application #:
11702847
Filing Dt:
02/05/2007
Publication #:
Pub Dt:
03/13/2008
Title:
Dual charge storage node with undercut gate oxide for deep sub-micron memory cell
82
Patent #:
Issue Dt:
03/27/2012
Application #:
11712299
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
09/13/2007
Title:
SEMICONDUCTOR DEVICE HAVING LOWER LEAKAGE CURRENT BETWEEN SEMICONDUCTOR SUBSTRATE AND BIT LINES
83
Patent #:
Issue Dt:
07/14/2009
Application #:
11724711
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
06/26/2008
Title:
CYCLING IMPROVEMENT USING HIGHER ERASE BIAS
84
Patent #:
Issue Dt:
04/19/2016
Application #:
11724725
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
07/03/2008
Title:
Dielectric extension to mitigate short channel effects
85
Patent #:
Issue Dt:
06/30/2009
Application #:
11724726
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
06/26/2008
Title:
USING IMPLANTED POLY-1 TO IMPROVE CHARGING PROTECTION IN DUAL-POLY PROCESS
86
Patent #:
Issue Dt:
12/27/2011
Application #:
11724773
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
07/03/2008
Title:
MULTI-STATE RESISTANCE CHANGING MEMORY WITH A WORD LINE DRIVER FOR APPLYING A SAME PROGRAM VOLTAGE TO THE WORD LINE
87
Patent #:
Issue Dt:
07/14/2009
Application #:
11724774
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
07/24/2008
Title:
METHODS AND SYSTEMS FOR RECOVERING DATA IN A NONVOLATILE MEMORY ARRAY
88
Patent #:
Issue Dt:
02/15/2011
Application #:
11724775
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
06/26/2008
Title:
USING THICK SPACER FOR BITLINE IMPLANT THEN REMOVE
89
Patent #:
Issue Dt:
07/13/2010
Application #:
11724788
Filing Dt:
03/16/2007
Publication #:
Pub Dt:
07/24/2008
Title:
NON-VOLATILE RESISTANCE CHANGING FOR ADVANCED MEMORY APPLICATIONS
90
Patent #:
NONE
Issue Dt:
Application #:
11735229
Filing Dt:
04/13/2007
Publication #:
Pub Dt:
06/26/2008
Title:
INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM
91
Patent #:
NONE
Issue Dt:
Application #:
11735241
Filing Dt:
04/13/2007
Publication #:
Pub Dt:
06/26/2008
Title:
MEMORY SYSTEM WITH POLY METAL GATE
92
Patent #:
Issue Dt:
03/17/2009
Application #:
11741996
Filing Dt:
04/30/2007
Publication #:
Pub Dt:
10/30/2008
Title:
TRANSFER OF NON-ASSOCIATED INFORMATION ON FLASH MEMORY DEVICES
93
Patent #:
Issue Dt:
08/17/2010
Application #:
11741998
Filing Dt:
04/30/2007
Publication #:
Pub Dt:
10/30/2008
Title:
METHOD TO OBTAIN MULTIPLE GATE THICKNESSES USING IN-SITU GATE ETCH MASK APPROACH
94
Patent #:
Issue Dt:
10/05/2010
Application #:
11742003
Filing Dt:
04/30/2007
Publication #:
Pub Dt:
10/30/2008
Title:
TRIPLE POLY-SI REPLACEMENT SCHEME FOR MEMORY DEVICES
95
Patent #:
Issue Dt:
03/02/2010
Application #:
11742371
Filing Dt:
04/30/2007
Publication #:
Pub Dt:
10/30/2008
Title:
ADAPTIVE DETECTION OF THRESHOLD LEVELS IN MEMORY
96
Patent #:
Issue Dt:
12/01/2009
Application #:
11745327
Filing Dt:
05/07/2007
Publication #:
Pub Dt:
11/13/2008
Title:
MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY
97
Patent #:
Issue Dt:
03/23/2010
Application #:
11746122
Filing Dt:
05/09/2007
Publication #:
Pub Dt:
11/13/2008
Title:
SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE
98
Patent #:
Issue Dt:
06/22/2010
Application #:
11747608
Filing Dt:
05/11/2007
Publication #:
Pub Dt:
11/13/2008
Title:
MANAGING FLASH MEMORY BASED UPON USAGE HISTORY
99
Patent #:
Issue Dt:
05/11/2010
Application #:
11748215
Filing Dt:
05/14/2007
Publication #:
Pub Dt:
06/26/2008
Title:
VARIABLE SALICIDE BLOCK FOR RESISTANCE EQUALIZATION IN AN ARRAY
100
Patent #:
Issue Dt:
08/07/2012
Application #:
11748743
Filing Dt:
05/15/2007
Publication #:
Pub Dt:
11/20/2008
Title:
METHODS OF FORMING SILICIDES OF DIFFERENT THICKNESSES ON DIFFERENT STRUCTURES
Assignors
1
Exec Dt:
05/10/2010
2
Exec Dt:
05/10/2010
3
Exec Dt:
05/10/2010
4
Exec Dt:
05/10/2010
Assignee
1
745 SEVENTH AVENUE
NEW YORK, NEW YORK 10019
Correspondence name and address
LATHAM & WATKINS, C/O JULIE DALKE
650 TOWN CENTER DR, 20TH FLOOR
042243-0080
COSTA MESA, CA 92626

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