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Patent #:
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Issue Dt:
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09/04/2001
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09495216
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01/31/2000
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Title:
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Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells
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Issue Dt:
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12/12/2000
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09498205
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02/04/2000
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Title:
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Noise reduction during simultaneous operation of a flash memory device
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07/31/2001
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09500699
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02/09/2000
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Title:
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Memory system having a program and erase voltage modifier
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06/05/2001
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09501159
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02/09/2000
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Title:
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Voltage boost reset circuit for a flash memory
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Issue Dt:
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04/10/2001
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09501448
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02/10/2000
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Title:
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Simultaneous program, program-verify scheme
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Issue Dt:
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02/19/2002
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09502153
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02/11/2000
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Title:
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Method of forming self-aligned contacts using consumable spacers
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07/16/2002
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09502163
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02/11/2000
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Title:
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SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
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01/27/2004
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09504087
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02/15/2000
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INTEGRATED CIRCUIT HAVING INCREASED GATE COUPLING CAPACITANCE
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06/05/2001
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09504186
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02/15/2000
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Title:
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Two-stage pipeline sensing for page mode flash memory
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Issue Dt:
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03/20/2001
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09504558
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02/15/2000
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Title:
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System and method for detecting flash memory threshold voltages
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Issue Dt:
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07/24/2001
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09504695
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02/16/2000
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Title:
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Method of erasing non-volatile memory cells
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Issue Dt:
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04/10/2001
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09504696
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02/16/2000
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Title:
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Method of maintaining constant erasing speeds for non-volatile memory cells
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Issue Dt:
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06/05/2001
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09505259
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02/16/2000
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Title:
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Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell
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09/24/2002
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09506298
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02/17/2000
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Title:
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ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
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09/04/2001
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09506351
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02/17/2000
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Title:
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High speed sensing to detect write protect state in a flash memory device
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06/25/2002
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09507810
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02/22/2000
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Title:
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METHOD FOR REMOVING SEMICONDUCTOR ARC USING ARC CMP BUFFING
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06/12/2001
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09511652
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02/22/2000
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Title:
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Symmetrical program and erase scheme to improve erase time degradation in NAND devices
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01/29/2002
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09511874
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02/25/2000
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Title:
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Variable pulse width memory programming
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05/01/2001
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09512617
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02/25/2000
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Title:
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High speed, high precision, power supply and process independent boost level clamping technique
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03/20/2001
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09512854
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02/25/2000
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Title:
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Dynamic memory cell programming voltage
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07/23/2002
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09513027
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02/25/2000
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Title:
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USER SELECTABLE CELL PROGRAMMING
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04/23/2002
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09513260
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02/24/2000
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Title:
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DOUBLE SELF-ALIGNING SHALLOW TRENCH ISOLATION SEMICONDUCTOR AND MANUFACTURING METHOD THEREFOR
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09/10/2002
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09513261
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02/24/2000
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Title:
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SEMICONDUCTOR WITH INCREASED GATE COUPLING COEFFICIENT
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Patent #:
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10/02/2001
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09513402
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02/25/2000
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Title:
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MODE INDICATOR FOR MULTI-LEVEL MEMORY
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04/17/2001
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09513643
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02/25/2000
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Multilevel cell programming
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04/27/2004
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09513698
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02/25/2000
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Title:
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DATA RECYCLING IN MEMORY
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Issue Dt:
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10/16/2001
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09514404
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02/28/2000
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Title:
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Register driven means to control programming voltages
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Issue Dt:
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06/12/2001
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09514560
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02/28/2000
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Title:
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System for erasing a memory cell
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Issue Dt:
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09/25/2001
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09514933
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02/28/2000
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Title:
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System for programming memory cells
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Issue Dt:
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03/27/2001
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09516472
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03/01/2000
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Title:
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FLASH MEMORY CELLS HAVING A MODULATION DOPED HETEROJUNCTION STRUCTURE
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Issue Dt:
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03/16/2004
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09516478
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03/01/2000
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INTERLACED MULTI-LEVEL MEMORY
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08/06/2002
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09522247
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03/09/2000
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Title:
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NAND FLASH MEMORY WITH SPECIFIED GATE OXIDE THICKNESS
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Patent #:
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09/04/2001
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09523816
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03/13/2000
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Wordline voltage protection
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Issue Dt:
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09/16/2003
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09525078
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03/14/2000
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Title:
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CHAINED ARRAY OF SEQUENTIAL ACCESS MEMORIES ENABLING CONTINUOUS READ
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05/29/2001
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09526239
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03/15/2000
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Title:
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Multiple bank simultaneous operation for a flash memory
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Issue Dt:
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11/06/2001
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09531582
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03/21/2000
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Title:
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Elimination of poly cap for easy poly 1 contact for nand product
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Issue Dt:
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11/13/2001
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09531749
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03/20/2000
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Title:
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A METHOD OF FORMING A NAND -TYPE FLASH MEMORY DEVICE H AVING A NON-STACKED SELECT GATE TRANSISTOR STRUCTURE
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04/01/2003
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09531871
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03/21/2000
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METHOD AND APPARATUS FOR EQUALIZATION OF ADDRESS TRANSITION DETECTION PULSE WIDTH
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11/26/2002
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09532293
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03/23/2000
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Title:
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FLASH MEMORY WITH LESS SUSCEPTIBILITY TO CHARGE GAIN AND CHARGE LOSS
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11/12/2002
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09532347
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03/21/2000
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METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE USING HIGH TEMPERATURE DESCUM
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02/26/2002
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09533057
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03/22/2000
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High voltage transistor with modified field implant mask
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Issue Dt:
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10/21/2003
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09533617
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03/22/2000
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METHOD AND SYSTEM FOR REDUCING CHARGE GAIN AND CHARGE LOSS IN INTERLAYER DIELECTRIC FORMATION
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04/09/2002
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09534507
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03/24/2000
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METHOD FOR FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
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08/13/2002
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09535255
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03/23/2000
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METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE LAYERS BY REDUCING DESCUM INDUCED DEFECTS
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10/08/2002
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09535256
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03/23/2000
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Pub Dt:
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05/16/2002
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Title:
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METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE LAYERS BY REDUCING DESCUM INDUCED DEFECTS
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02/12/2002
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09538168
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03/30/2000
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Title:
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Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation
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10/23/2001
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09538922
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03/30/2000
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Title:
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Method and system for fabricating a flash memory array
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09/10/2002
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09539307
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03/30/2000
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Title:
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METHOD AND SYSTEM FOR PROCESSING A SEMICONDUCTOR DEVICE
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03/11/2003
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09543484
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04/06/2000
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USE OF GASEOUS SILICON HYDRIDES AS A REDUCING AGENT TO REMOVE RE-SPUTTERED SILICON OXIDE
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05/15/2001
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09543991
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04/06/2000
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Title:
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New method to fabricate a high coupling flash cell with less silicide seam problem
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03/27/2001
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Application #:
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09547556
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04/12/2000
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Address transition detect timing architecture for a simultaneous operation flash memory device
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08/06/2002
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09547660
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04/12/2000
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TRIMMING METHOD AND SYSTEM FOR WORDLINE BOOSTER TO MINIMIZE PROCESS VARIATION OF BOOSTED WORDLINE VOLTAGE
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07/31/2001
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09547747
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04/12/2000
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Charge sharing to help boost the wordlines during apde verify
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03/18/2003
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09548616
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04/13/2000
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METHOD OF HIGH DENSITY PLASMA METAL ETCHING
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02/26/2002
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09548741
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04/13/2000
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Interlevel dielectric thickness monitor for complex semiconductor chips
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Issue Dt:
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07/10/2001
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09557728
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04/26/2000
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Title:
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Matching loading between sensing reference and memory cell with reduced transistor count in a dual-bank flash memory
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04/24/2001
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09557832
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04/26/2000
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Title:
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Auto adjusting window placement scheme for an NROM virtual ground array
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03/13/2001
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Application #:
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09558764
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04/26/2000
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Title:
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Apparatus and method to characterize the threshold distribution in an nrom virtual ground array
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05/15/2001
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09562442
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05/01/2000
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Title:
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Methodology for achieving dual gate oxide thicknesses
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04/02/2002
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09563024
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05/02/2000
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Title:
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Submicron semiconductor device having a self-aligned channel stop region and a method for fabricating the semiconductor device using a trim and etch
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08/26/2003
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09563179
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05/02/2000
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FLASH MEMORY ARRAY AND A METHOD AND SYSTEM OF FABRICATION THEREOF
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09/03/2002
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09563797
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05/02/2000
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METHOD AND SYSTEM FOR PROVIDING CONTACTS WITH GREATER TOLERANCE FOR MISALIGNMENT IN A FLASH MEMORY
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10/23/2001
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09567534
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05/10/2000
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Multipurpose graded silicon oxynitride cap layer
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09/25/2001
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09586254
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05/31/2000
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Title:
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Semiconductor manufacturing method using a high extinction coefficient dielectric photomask
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02/19/2002
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09586264
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05/31/2000
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Title:
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Method for using a low dielectric constant layer as a semiconductor anti-reflective coating
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04/23/2002
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09588117
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05/31/2000
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METHOD FOR ELIMINATING ANTI-REFLECTIVE COATING IN SEMICONDUCTORS
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04/30/2002
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09588119
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05/31/2000
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Title:
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METHOD FOR CREATING PARTIALLY UV TRANSPARENT ANTI-REFLECTIVE COATING FOR SEMICONDUCTORS
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03/19/2002
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09592474
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06/09/2000
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Activation of wordline decoders to transfer a high voltage supply
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Issue Dt:
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03/27/2001
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Application #:
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09593303
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Filing Dt:
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06/13/2000
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Title:
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Method to reduce capactive loading in flash memory x-decoder for accurate voltage control at wordlines and select lines
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01/28/2003
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09594207
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06/14/2000
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FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER AND METHOD OF FORMING
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10/23/2001
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09595166
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06/15/2000
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Title:
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Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming
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02/26/2002
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09595519
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06/16/2000
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Title:
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Voltage boost level clamping circuit for a flash memory
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07/17/2001
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09596449
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06/19/2000
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Title:
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Dual bit isolation scheme for flash devices
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Issue Dt:
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03/12/2002
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Application #:
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09597358
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Filing Dt:
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06/19/2000
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Title:
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Dual bit isolation scheme for flash devices
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09602095
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Filing Dt:
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06/22/2000
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Title:
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Voltage protection of write protect cams
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09602328
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Filing Dt:
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06/23/2000
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Title:
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Apparatus and method of direct current sensing from source side in a virtual ground array
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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09607675
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Filing Dt:
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06/30/2000
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Title:
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DUAL-PURPOSE ANTI-REFLECTIVE COATING AND SPACER FOR FLASH MEMORY AND OTHER DUAL GATE TECHNOLOGIES AND METHOD OF FORMING
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09609468
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Filing Dt:
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07/03/2000
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Title:
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Species implantation for minimizing interface defect density in flash memory devices
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09609793
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Filing Dt:
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07/03/2000
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Title:
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AUTOMATED DETERMINATION AND DISPLAY OF THE PHYSICAL LOCATION OF A FAILED CELL IN AN ARRAY OF MEMORY CELLS
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09610764
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Filing Dt:
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07/06/2000
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Title:
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Temperature-compensated bias generator
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09617820
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Filing Dt:
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07/17/2000
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Title:
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Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09619231
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Filing Dt:
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07/19/2000
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Title:
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ELIMINATION OF N+ CONTACT IMPLANT FROM FLASH TECHNOLOGIES BY REPLACEMENT WITH STANDARD DOUBLE-DIFFUSED AND N+ IMPLANTS
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09620339
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Filing Dt:
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07/20/2000
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Title:
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Fully recessed semiconductor method for low power applications
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Patent #:
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Issue Dt:
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06/25/2002
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Application #:
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09620480
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Filing Dt:
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07/20/2000
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Title:
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PROCESS FOR OPTIMIZING POCKET IMPLANT PROFILE BY RTA IMPLANT ANNEALING FOR A NON-VOLATILE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09627563
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Filing Dt:
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07/28/2000
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Title:
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INTEGRATION OF AN ION IMPLANT HARD MASK STRUCTURE INTO A PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09627565
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Filing Dt:
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07/28/2000
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Title:
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Dual bit isolation scheme for flash memory devices having polysilicon floating gates
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09627567
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Filing Dt:
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07/28/2000
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Title:
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Use of an etch to reduce the thickness and round the edges of a resist mask during the creation of a memory cell
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09627584
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Filing Dt:
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07/28/2000
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Title:
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Optimization of thermal cycle for the formation of pocket implants
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09627664
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Filing Dt:
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07/28/2000
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Title:
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Nitrogen implant after bit-line formation for ono flash memory devices
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09628130
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Filing Dt:
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07/28/2000
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Title:
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PROCESS FOR CREATING A FLASH MEMORY CELL USING A PHOTORESIST FLOW OPERATION
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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09629780
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Filing Dt:
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07/31/2000
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Title:
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TRENCHED GATE NON-VOLATILE SEMICONDUCTOR METHOD WITH THE SOURCE/DRAIN REGIONS SPACED FROM THE TRENCH BY SIDEWALL DOPINGS
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Patent #:
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Issue Dt:
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09/10/2002
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Application #:
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09631894
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Filing Dt:
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08/04/2000
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Title:
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NOVEL CAPPING LAYER
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09632390
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Filing Dt:
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08/04/2000
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Title:
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REDUNDANT DUAL BANK ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09632536
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Filing Dt:
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08/04/2000
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Title:
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A TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS WITH CORNER DOPING AND SIDEWALL DOPING
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09634991
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Filing Dt:
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08/08/2000
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Title:
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SOURCE BUS FORMATION FOR A FLASH MEMORY USING SILICIDE
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09636333
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Filing Dt:
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08/10/2000
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Title:
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SELF-ALIGNED GATE SEMICONDUCTOR
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09638055
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Filing Dt:
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08/11/2000
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Title:
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Burst read mode word line boosting
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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09639798
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Filing Dt:
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08/17/2000
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Title:
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MASK FOR AND METHOD OF FORMING A CHARACTER ON A SUBSTRATE
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Patent #:
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Issue Dt:
|
11/05/2002
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Application #:
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09640082
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Filing Dt:
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08/17/2000
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Title:
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OXYGEN IMPLANTATION FOR REDUCTION OF JUNCTION CAPACITANCE IN MOS TRANSISTORS
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|
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Patent #:
|
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Issue Dt:
|
12/04/2001
|
Application #:
|
09644358
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Filing Dt:
|
08/23/2000
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|
Title:
|
Precise reference wordline loading compensation for a high density flash memory device
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