|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2004
|
Application #:
|
10022292
|
Filing Dt:
|
12/15/2001
|
|
Title:
|
METHOD FOR MANUFACTURING MEMORY WITH HIGH CONDUCTIVITY BITLINE AND SHALLOW TRENCH ISOLATION INTEGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10022798
|
Filing Dt:
|
12/20/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2003
| | | | |
|
Title:
|
MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
10023349
|
Filing Dt:
|
12/20/2001
|
|
Title:
|
METHOD FOR REPAIRING DAMAGE TO CHARGE TRAPPING DIELECTRIC LAYER FROM BIT LINE IMPLANTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
10023436
|
Filing Dt:
|
12/15/2001
|
|
Title:
|
FLASH MEMORY WITH CONTROLLED WORDLINE WIDTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
10027253
|
Filing Dt:
|
12/20/2001
|
|
Title:
|
FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10030117
|
Filing Dt:
|
01/23/2002
|
|
Title:
|
MULTIPLE-BIT NON-VOLATILE MEMORY UTILIZING NON-CONDUCTIVE CHARGE TRAPPING GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
10032630
|
Filing Dt:
|
12/27/2001
|
|
Title:
|
SHALLOW TRENCH ISOLATION SPACER FOR WEFF IMPROVEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2004
|
Application #:
|
10032646
|
Filing Dt:
|
12/27/2001
|
|
Title:
|
PLANAR TRANSISTOR STRUCTURE USING ISOLATION IMPLANTS FOR IMPROVED VSS RESISTANCE AND FOR PROCESS SIMPLIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10032757
|
Filing Dt:
|
12/27/2001
|
|
Title:
|
METHOD AND SYSTEM FOR FORMING DUAL GATE STRUCTURES IN A NONVOLATILE MEMORY USING A PROTECTIVE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2004
|
Application #:
|
10036757
|
Filing Dt:
|
12/31/2001
|
|
Title:
|
USE OF HIGH-K DIELECTRIC MATERIALS IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2002
|
Application #:
|
10043114
|
Filing Dt:
|
01/14/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/24/2002
| | | | |
|
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
10044510
|
Filing Dt:
|
01/11/2002
|
|
Title:
|
METHOD OF MANUFACTURING HIGH VOLTAGE TRANSISTOR WITH MODIFIED FIELD IMPLANT MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
|
10045354
|
Filing Dt:
|
11/07/2001
|
|
Title:
|
INNOVATIVE METHOD OF HARD MASK REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
10050254
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
NEGATIVE PUMP REGULATOR USING MOS CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
10050257
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
SOURCE SIDE SENSING SCHEME FOR VIRTUAL GROUND READ OF FLASH EPROM ARRAY WITH ADJACENT BIT PRECHARGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10050342
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
METHOD AND APPARATUS FOR PRE-CHARGING NEGATIVE PUMP MOS REGULATION CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
10050394
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
DIODE FABRICATION FOR ESD/EOS PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
10050483
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
CHARGE INJECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
10050650
|
Filing Dt:
|
01/16/2002
|
|
Title:
|
METHOD AND APPARATUS FOR SOFT PROGRAM VERIFICATION IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
10052484
|
Filing Dt:
|
01/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
METHOD AND DEVICE FOR READING DUAL BIT MEMORY CELLS USING MULTIPLE REFERENCE CELLS WITH TWO SIDE READ
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10053256
|
Filing Dt:
|
01/18/2002
|
|
Title:
|
TWO-STEP SOURCE SIDE IMPLANT FOR IMPROVING SOURCE RESISTANCE AND SHORT CHANNEL EFFECT IN DEEP SUB-0.18MUM FLASH MEMORY TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2003
|
Application #:
|
10061620
|
Filing Dt:
|
02/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
|
Title:
|
POWER-SAVING MODES FOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
10067765
|
Filing Dt:
|
02/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
|
Title:
|
PLANARIZATION OF A POLYSILICON LAYER SURFACE BY CHEMICAL MECHANICAL POLISH TO IMPROVE LITHOGRAPHY AND SILICIDE FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2003
|
Application #:
|
10069124
|
Filing Dt:
|
03/01/2002
|
|
Title:
|
NONVOLATILE MEMORY CIRCUIT FOR RECORDING MULTIPLE BIT INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2004
|
Application #:
|
10074495
|
Filing Dt:
|
02/11/2002
|
|
Title:
|
PARTIAL PAGE PROGRAMMING OF MULTI LEVEL FLASH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
10077778
|
Filing Dt:
|
02/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
08/29/2002
| | | | |
|
Title:
|
MEMORY DEVICE FOR CONTROLLING NONVOLATILE AND VOLATILE MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10079775
|
Filing Dt:
|
02/19/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
METHOD FOR REDUCING ANTI-REFLECTIVE COATING LAYER REMOVAL DURING REMOVAL OF PHOTORESIST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
10081246
|
Filing Dt:
|
02/22/2002
|
|
Title:
|
DUMMY GATE PROCESS TO REDUCE THE VSS RESISTANCE OF FLASH PRODUCTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
10083789
|
Filing Dt:
|
02/27/2002
|
|
Title:
|
METHOD OF MATCHING CORE CELL AND REFERENCE CELL SOURCE RESISTANCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10085023
|
Filing Dt:
|
03/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/04/2002
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10086112
|
Filing Dt:
|
02/27/2002
|
|
Title:
|
NROM CELL WITH N-LESS CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
10091767
|
Filing Dt:
|
03/07/2002
|
|
Title:
|
PASSWORD AND DYNAMIC PROTECTION OF FLASH MEMORY DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2004
|
Application #:
|
10095512
|
Filing Dt:
|
03/12/2002
|
|
Title:
|
MEMORY ARRAY WITH BURIED BIT LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10095739
|
Filing Dt:
|
03/12/2002
|
|
Title:
|
LOW COLUMN LEAKAGE FLASH MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
10096313
|
Filing Dt:
|
03/12/2002
|
|
Title:
|
FLASH MEMORY ARRAY ARCHITECTURE HAVING STAGGERED METAL LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
|
Application #:
|
10096338
|
Filing Dt:
|
03/11/2002
|
|
Publication #:
|
|
Pub Dt:
|
09/11/2003
| | | | |
|
Title:
|
SYSTEM FOR SETTING MEMORY VOLTAGE THRESHOLD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10096741
|
Filing Dt:
|
03/14/2002
|
|
Title:
|
LASER THERMAL ANNEALING OF SILICON NITRIDE FOR INCREASED DENSITY AND ETCH SELECTIVITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10097499
|
Filing Dt:
|
03/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2003
| | | | |
|
Title:
|
MEMORY CONTROLLER FOR MULTILEVEL CELL MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
10097912
|
Filing Dt:
|
03/13/2002
|
|
Title:
|
USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
10097924
|
Filing Dt:
|
03/15/2002
|
|
Publication #:
|
|
Pub Dt:
|
07/18/2002
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY AND ITS USAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2003
|
Application #:
|
10099499
|
Filing Dt:
|
03/13/2002
|
|
Title:
|
OVERERASE CORRECTION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
10100485
|
Filing Dt:
|
03/14/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
10100487
|
Filing Dt:
|
03/14/2002
|
|
Title:
|
MEMORY WITH DISPOSABLE ARC FOR WORDLINE FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
10103077
|
Filing Dt:
|
03/20/2002
|
|
Title:
|
MEMORY DEVICE HAVING IMPROVED PROGRAMMABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10103557
|
Filing Dt:
|
03/22/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/20/2003
| | | | |
|
Title:
|
ULTRAVIOLET-LIGHT IRRADIATION APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2004
|
Application #:
|
10109234
|
Filing Dt:
|
03/27/2002
|
|
Title:
|
LINER FOR SEMICONDUCTOR MEMORIES AND MANUFACTURING METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
10109235
|
Filing Dt:
|
03/27/2002
|
|
Title:
|
MEMORY WORDLINE HARD MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
10109516
|
Filing Dt:
|
03/27/2002
|
|
Title:
|
METHOD OF MAKING MEMORY WORDLINE HARD MASK EXTENSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
10109526
|
Filing Dt:
|
03/27/2002
|
|
Title:
|
METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
10112976
|
Filing Dt:
|
03/28/2002
|
|
Title:
|
A TEST STRUCTURE APPARATUS FOR MEASURING STANDBY CURRENT IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10113017
|
Filing Dt:
|
03/28/2002
|
|
Title:
|
METHOD OF DETERMINING LOCATION OF GATE OXIDE BREAKDOWN OF MOSFET BY MEASURING CURRENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10113152
|
Filing Dt:
|
03/28/2002
|
|
Title:
|
METHOD OF DETECTING SHALLOW TRENCH ISOLATION CORNER THINNING BY ELECTRICAL STRESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10113259
|
Filing Dt:
|
03/28/2002
|
|
Title:
|
METHOD OF DETECTING SHALLOW TRENCH ISOLATION CORNER THINNING BY ELECTRICAL TRAPPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10117818
|
Filing Dt:
|
04/08/2002
|
|
Title:
|
PRECISION HIGH-K INTERGATE DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2004
|
Application #:
|
10118363
|
Filing Dt:
|
04/08/2002
|
|
Title:
|
STACKED POLYSILICON LAYER FOR BORON PENETRATION INHIBITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
|
Application #:
|
10119273
|
Filing Dt:
|
04/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2003
| | | | |
|
Title:
|
REFRESH SCHEME FOR DYNAMIC PAGE PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2005
|
Application #:
|
10119366
|
Filing Dt:
|
04/08/2002
|
|
Title:
|
ERASE METHOD FOR A DUAL BIT MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2004
|
Application #:
|
10119391
|
Filing Dt:
|
04/08/2002
|
|
Title:
|
ALGORITHM DYNAMIC REFERENCE PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10120116
|
Filing Dt:
|
04/09/2002
|
|
Title:
|
ISOLATION TRENCH FILL PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
10121140
|
Filing Dt:
|
04/11/2002
|
|
Title:
|
METHODS AND SYSTEMS FOR FLASH MEMORY TUNNEL OXIDE RELIABILITY TESTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10126193
|
Filing Dt:
|
04/19/2002
|
|
Title:
|
METHOD OF DETECTING AND DISTINGUISHING STACK GATE EDGE DEFECTS AT THE SOURCE OR DRAIN JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
10126207
|
Filing Dt:
|
04/19/2002
|
|
Title:
|
USING A FIRST LINER LAYER AS A SPACER IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2004
|
Application #:
|
10126280
|
Filing Dt:
|
04/19/2002
|
|
Title:
|
MEMORY MANUFACTURING PROCESS USING DISPOSABLE ARC FOR WORDLINE FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
10126326
|
Filing Dt:
|
04/19/2002
|
|
Title:
|
RELACS SHRINK METHOD APPLIED FOR SINGLE PRINT RESIST MASK FOR LDD OR BURIED BITLINE IMPLANTS USING CHEMICALLY AMPLIFIED DUV TYPE PHOTORESIST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
10126330
|
Filing Dt:
|
04/19/2002
|
|
Title:
|
PROGRAMMING WITH FLOATING SOURCE FOR LOW POWER, LOW LEAKAGE AND HIGH DENSITY FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
10126363
|
Filing Dt:
|
04/19/2002
|
|
Title:
|
NOVEL METHOD TO DISTINGUISH AN STI OUTER EDGE CURRENT COMPONENT WITH AN STI NORMAL CURRENT COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10126814
|
Filing Dt:
|
04/19/2002
|
|
Title:
|
METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON THIN GATE OXIDES TO IMPROVE PERIPHERAL TRANSISTOR RELIABILITY AND PERFORMANCE FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2004
|
Application #:
|
10126840
|
Filing Dt:
|
04/19/2002
|
|
Title:
|
METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON TUNNEL OXIDES USING PARTIAL NITRIDE STRIP AND SMALL BIRD'S BEAK FORMATION FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2004
|
Application #:
|
10126841
|
Filing Dt:
|
04/19/2002
|
|
Title:
|
REPLACING A FIRST LINER LAYER WITH A THICKER OXIDE LAYER WHEN FORMING A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10128771
|
Filing Dt:
|
04/22/2002
|
|
Title:
|
SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
10136033
|
Filing Dt:
|
04/29/2002
|
|
Title:
|
SYSTEM FOR PROGRAMMING A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2004
|
Application #:
|
10136034
|
Filing Dt:
|
04/29/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2003
| | | | |
|
Title:
|
SYSTEM FOR CONTROL OF PRE-CHARGE LEVELS IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2004
|
Application #:
|
10136173
|
Filing Dt:
|
05/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2003
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10139745
|
Filing Dt:
|
05/07/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/07/2002
| | | | |
|
Title:
|
MEMORY DEVICE WITH A SELF-ASSEMBLED POLYMER FILM AND METHOD OF MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
10143449
|
Filing Dt:
|
05/10/2002
|
|
Title:
|
SYSTEM FOR READING A DOUBLE-BIT MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2004
|
Application #:
|
10145952
|
Filing Dt:
|
05/15/2002
|
|
Title:
|
REPLACING LAYERS OF AN INTERGATE DIELECTRIC LAYER WITH HIGH-K MATERIAL FOR IMPROVED SCALABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10146074
|
Filing Dt:
|
05/16/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
METHOD FOR ERROR DETECTION/CORRECTION OF MULTILEVEL CELL MEMORY AND MULTILEVEL CELL MEMORY HAVING ERROR DETECTION/CORRECTION FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
10147622
|
Filing Dt:
|
05/16/2002
|
|
Title:
|
NON-VOLATILE MEMORY DIELECTRIC AS CHARGE PUMP DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2003
|
Application #:
|
10150204
|
Filing Dt:
|
05/15/2002
|
|
Title:
|
SELF-ALIGNED POLYSILICON POLISH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2004
|
Application #:
|
10150240
|
Filing Dt:
|
05/15/2002
|
|
Title:
|
METHOD AND SYSTEM FOR TAILORING CORE AND PERIPHERY CELLS IN A NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10150255
|
Filing Dt:
|
05/15/2002
|
|
Title:
|
METHOD AND SYSTEM FOR SCALING NONVOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
10150282
|
Filing Dt:
|
05/15/2002
|
|
Title:
|
METHOD FOR MINIMIZING NITRIDE RESIDUE ON A SILICON WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2002
|
Application #:
|
10150556
|
Filing Dt:
|
05/17/2002
|
|
Title:
|
METHOD FOR FABRICATING SELF-ALIGNED GATE OF FLASH MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2003
|
Application #:
|
10151576
|
Filing Dt:
|
05/16/2002
|
|
Title:
|
MEMORY MANUFACTURING PROCESS USING BITLINE RAPID THERMAL ANNEAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10151595
|
Filing Dt:
|
05/16/2002
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TRENCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
10152747
|
Filing Dt:
|
05/21/2002
|
|
Title:
|
METHOD OF FORMING LOW RESISTANCE COMMON SOURCE LINE FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2003
|
Application #:
|
10155500
|
Filing Dt:
|
05/23/2002
|
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING A POLYSILICON STRINGER MONITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2004
|
Application #:
|
10158044
|
Filing Dt:
|
05/30/2002
|
|
Title:
|
NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN FABRICATION OF SONOS FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10159078
|
Filing Dt:
|
05/31/2002
|
|
Title:
|
SEMICONDUCTOR ISOLATION MATERIAL DEPOSITION SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
10159323
|
Filing Dt:
|
05/31/2002
|
|
Title:
|
METHOD FOR INCREASING CORE GAIN IN FLASH MEMORY DEVICE USING STRAINED SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10160050
|
Filing Dt:
|
06/04/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/17/2002
| | | | |
|
Title:
|
METHOD OF DRIVING A SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
10164895
|
Filing Dt:
|
06/07/2002
|
|
Title:
|
HIGH DENSITY DUAL BIT FLASH MEMORY CELL WITH NON PLANAR STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10165383
|
Filing Dt:
|
06/06/2002
|
|
Title:
|
METHOD AND SYSTEM FOR DETERMINING FLOW RATES FOR CONTACT FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2003
|
Application #:
|
10165837
|
Filing Dt:
|
06/06/2002
|
|
Title:
|
HARD MASK REMOVAL PROCESS INCLUDING ISOLATION DIELECTRIC REFILL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
|
Application #:
|
10173262
|
Filing Dt:
|
06/17/2002
|
|
Title:
|
HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
10174550
|
Filing Dt:
|
06/18/2002
|
|
Title:
|
SHALLOW TRENCH ISOLATION FILL PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2004
|
Application #:
|
10174734
|
Filing Dt:
|
06/18/2002
|
|
Title:
|
TEST STRUCTURE TO MEASURE INTERLAYER DIELECTRIC EFFECTS AND BREAKDOWN AND DETECT METAL DEFECTS IN FLASH MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2003
|
Application #:
|
10176594
|
Filing Dt:
|
06/21/2002
|
|
Title:
|
USE OF HIGH-K DIELECTRIC MATERIAL FOR ONO AND TUNNEL OXIDE TO IMPROVE FLOATING GATE FLASH MEMORY COUPLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2003
|
Application #:
|
10178106
|
Filing Dt:
|
06/24/2002
|
|
Title:
|
INNOVATIVE NARROW GATE FORMATION FOR FLOATING GATE FLASH TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2003
|
Application #:
|
10178144
|
Filing Dt:
|
06/24/2002
|
|
Title:
|
EXTRACTION OF DRAIN JUNCTION OVERLAP WITH THE GATE AND THE CHANNEL LENGTH FOR ULTRA-SMALL CMOS DEVICES WITH ULTRA-THIN GATE OXIDES
|
|
