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04/15/2003
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10179061
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Filing Dt:
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06/24/2002
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Title:
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NOVEL CAPPING LAYER
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Issue Dt:
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08/31/2004
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10179723
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Filing Dt:
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06/25/2002
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Title:
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PROCESS TO IMPROVE THE VSS LINE FORMATION FOR HIGH DENSITY FLASH MEMORY AND RELATED STRUCTURE ASSOCIATED THEREWITH
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Issue Dt:
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05/27/2003
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10180673
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Filing Dt:
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06/26/2002
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Title:
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2BIT/CELL ARCHITECTURE FOR FLOATING GATE FLASH MEMORY PRODUCT AND ASSOCIATED METHOD
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07/08/2003
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10180772
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Filing Dt:
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06/25/2002
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Title:
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CHARGE GAIN/CHARGE LOSS JUNCTION LEAKAGE PREVENTION FOR FLASH TECHNOLOGY BY USING DOUBLE ISOLATION/CAPPING LAYER BETWEEN LIGHTLY DOPED DRAIN AND GATE
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09/30/2003
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10189651
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07/03/2002
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Title:
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MEMORY DEVICE AND METHOD OF MAKING
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Issue Dt:
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05/30/2006
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10190002
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Filing Dt:
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07/03/2002
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Title:
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METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY ISOLATION MATERIAL GROWTH
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08/03/2004
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10190397
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Filing Dt:
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07/02/2002
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Title:
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METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY CMP STOP LAYER FORMATION
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02/22/2005
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10190420
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Filing Dt:
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07/03/2002
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Title:
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TEST STRUCTURE FOR MEASURING EFFECT OF TRENCH ISOLATION ON OXIDE IN A MEMORY DEVICE
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11/02/2004
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10197116
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07/16/2002
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01/22/2004
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Title:
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SYSTEM FOR USING A DYNAMIC REFERENCE IN A DOUBLE-BIT CELL MEMORY
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06/15/2004
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10199793
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Filing Dt:
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07/19/2002
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Title:
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NONVOLATILE MEMORY CELL WITH A NITRIDATED OXIDE LAYER
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Patent #:
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12/16/2003
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10200330
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Filing Dt:
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07/22/2002
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Title:
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ON-CHIP ERASE PULSE COUNTER FOR EFFICIENT ERASE VERIFY BIST (BUILT-IN-SELF-TEST) MODE
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Patent #:
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03/07/2006
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10200518
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07/22/2002
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Title:
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ADDRESS SEQUENCER WITHIN BIST (BUILT-IN-SELF-TEST) SYSTEM
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04/11/2006
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10200526
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07/22/2002
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Title:
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DIAGNOSTIC MODE FOR TESTING FUNCTIONALITY OF BIST (BUILT-IN-SELF-TEST) BACK-END STATE MACHINE
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03/16/2004
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10200539
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07/22/2002
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Title:
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GENERATION OF MARGINING VOLTAGE ON-CHIP DURING TESTING CAM PORTION OF FLASH MEMORY DEVICE
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Issue Dt:
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10/07/2003
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10200544
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07/22/2002
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Title:
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ON-CHIP REPAIR OF DEFECTIVE ADDRESS OF CORE FLASH MEMORY CELLS
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02/15/2005
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10207056
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07/30/2002
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06/05/2003
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Title:
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SEMICONDUCTOR MEMORY AND METHOD OF DRIVING THE SAME
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Patent #:
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Issue Dt:
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05/10/2005
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10210378
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Filing Dt:
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07/31/2002
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Title:
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SYSTEM AND METHOD FOR ERASE VOLTAGE CONTROL DURING MULTIPLE SECTOR ERASE OF A FLASH MEMORY DEVICE
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03/14/2006
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10211317
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08/05/2002
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Title:
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NON-VOLATILE MEMORY DEVICE
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Issue Dt:
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11/04/2003
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10215140
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08/07/2002
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Title:
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METHOD FOR REPAIRING OVER-ERASURE OF FAST BITS IN FLOATING GATE MEMORY DEVICES
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Issue Dt:
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10/26/2004
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10217403
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08/14/2002
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Title:
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REFLOWABLE-DOPED HDP FILM
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02/24/2004
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10217807
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Filing Dt:
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08/12/2002
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Title:
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METHOD OF PROTECTING A STACKED GATE STRUCTURE DURING FABRICATION
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Issue Dt:
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05/04/2004
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Application #:
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10217821
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Filing Dt:
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08/12/2002
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Title:
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
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Issue Dt:
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03/08/2005
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10217965
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08/12/2002
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Title:
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METHOD AND SYSTEM FOR DETECTING TUNNEL OXIDE ENCROACHMENT ON A MEMORY DEVICE
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11/01/2005
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10221682
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09/13/2002
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Pub Dt:
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03/13/2003
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Title:
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OPTICAL DISK HAVING SYNCHRONIZATION REGION FORMED BETWEEN PRE-RECORDED AREA AND RECORDABLE AREA
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Patent #:
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Issue Dt:
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04/29/2003
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10223195
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08/19/2002
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Pub Dt:
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12/19/2002
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Title:
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SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
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Issue Dt:
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04/15/2003
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Application #:
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10223486
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Filing Dt:
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08/19/2002
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Title:
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SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
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Issue Dt:
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06/22/2004
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10223920
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08/20/2002
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Title:
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MEMORY DEVICE AND METHOD OF MAKING
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Issue Dt:
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11/16/2004
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Application #:
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10224028
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08/19/2002
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Title:
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METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED
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Issue Dt:
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07/06/2004
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10224737
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08/20/2002
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Title:
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METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED
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Issue Dt:
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04/26/2005
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10225052
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Filing Dt:
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08/20/2002
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Title:
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METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED
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Issue Dt:
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08/03/2004
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10226912
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08/22/2002
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02/26/2004
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Title:
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PRECHARGING SCHEME FOR READING A MEMORY CELL
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Issue Dt:
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03/16/2004
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10230729
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08/29/2002
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Title:
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DUMMY WORDLINE FOR ERASE AND BITLINE LEAKAGE
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Issue Dt:
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12/07/2004
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10232487
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08/30/2002
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Title:
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FLOATING GATE MEMORY DEVICE WITH HOMOGENEOUS OXYNITRIDE TUNNELING DIELECTRIC
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06/01/2004
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10233906
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09/03/2002
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Title:
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FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS
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07/20/2004
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10237805
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09/10/2002
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01/09/2003
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Title:
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METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY AND NON-VOLATILE SEMICONDUCTOR MEMORY MANUFACTURED THEREBY
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04/06/2004
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10238412
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09/10/2002
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VIRTUAL GROUND SILICIDE BIT LINE PROCESS FOR FLOATING GATE FLASH MEMORY
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11/09/2004
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10238880
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09/11/2002
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03/20/2003
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Title:
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MEMORY DEVICE
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08/10/2004
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10243108
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09/13/2002
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Title:
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MEMORY WORDLINE SPACER
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11/28/2006
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10243315
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09/12/2002
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03/18/2004
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SYSTEM AND METHOD FOR Y-DECODING IN A FLASH MEMORY DEVICE
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04/27/2004
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10243433
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09/12/2002
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PATH GATE DRIVER CIRCUIT
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06/01/2004
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10243792
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09/12/2002
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Title:
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METHOD AND SYSTEM TO MINIMIZE PAGE PROGRAMMING TIME FOR FLASH MEMORY DEVICES
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09/30/2003
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10244129
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09/13/2002
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Title:
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A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-MICRON FLASH MEMORY SEMICONDUCTOR DEVICE
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12/09/2003
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10244229
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09/16/2002
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HIGH DENSITY FLOATING GATE FLASH MEMORY AND FABRICATION PROCESSES THEREFOR
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09/28/2004
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10244369
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09/16/2002
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METHODS FOR FABRICATING AND PLANARIZING DUAL POLY SCALABLE SONOS FLASH MEMORY
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06/22/2004
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10245146
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09/16/2002
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REFERENCE CELL WITH VARIOUS LOAD CIRCUITS COMPENSATING FOR SOURCE SIDE LOADING EFFECTS IN A NON-VOLATILE MEMORY
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05/24/2005
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10247641
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09/18/2002
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Title:
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A MULTI-BIT SILICON NITRIDE CHARGE-TRAPPING NON-VOLATILE MEMORY CELL
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08/03/2004
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10254381
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09/25/2002
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Title:
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IMPLEMENTING REFERENCE CURRENT MEASUREMENT MODE WITHIN REFERENCE ARRAY PROGRAMMING MODE OR REFERENCE ARRAY ERASE MODE IN A SEMICONDUCTOR
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Issue Dt:
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11/09/2004
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10260061
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09/27/2002
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FLASH MEMORY HAVING IMPROVED CORE FIELD ISOLATION IN SELECT GATE REGIONS
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Issue Dt:
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03/15/2005
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10262221
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09/30/2002
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Title:
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ORGANIC SPIN-ON ANTI-REFLECTIVE COATING OVER INORGANIC ANTI-REFLECTIVE COATING
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02/22/2005
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10264387
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10/04/2002
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Title:
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GROUND STRUCTURE FOR PAGE READ AND PAGE WRITE FOR FLASH MEMORY
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Issue Dt:
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12/21/2004
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10265001
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10/04/2002
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Title:
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METHOD FOR REDUCING DRAIN INDUCED BARRIER LOWERING IN A MEMORY DEVICE
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10/07/2003
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10274063
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10/17/2002
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BI-LAYER FLOATING GATE FOR IMPROVED WORK FUNCTION BETWEEN FLOATING GATE AND A HIGH-K DIELECTRIC LAYER
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10/21/2008
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10277395
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10/22/2002
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09/18/2003
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SHALLOW TRENCH ISOLATION APPROACH FOR IMPROVED STI CORNER ROUNDING
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08/24/2004
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10282459
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10/29/2002
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BUFFER DRIVER CIRCUIT FOR PRODUCING A FAST, STABLE, AND ACCURATE REFERENCE VOLTAGE
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06/22/2004
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10282847
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10/29/2002
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METHOD OF PROGRAMMING IN-SERIES MEMORY CELLS
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09/21/2004
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10283590
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10/30/2002
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METHOD FOR READING A NON-VOLATILE MEMORY CELL
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02/07/2006
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10283685
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10/29/2002
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SEMICONDUCTOR MANUFACTURING RESOLUTION ENHANCEMENT SYSTEM AND METHOD FOR SIMULTANEOUSLY PATTERNING DIFFERENT FEATURE TYPES
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12/28/2004
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10284769
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10/31/2002
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SYSTEM AND METHOD OF FORMING A PASSIVE LAYER BY A CMP PROCESS
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03/15/2005
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10284866
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10/30/2002
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05/06/2004
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NITROGEN OXIDATION TO REDUCE ENCROACHMENT
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05/31/2005
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10284946
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10/31/2002
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MULTI-CELL ORGANIC MEMORY ELEMENT AND METHODS OF OPERATING AND FABRICATING
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06/22/2004
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10285183
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10/31/2002
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MEMORY CELL FORMATION WITH PROCESS FOR PATTERNING CONDUCTING POLYMER FILMS
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11/16/2004
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10285909
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10/31/2002
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MEMORY DEVICE HAVING RESISTIVE ELEMENT COUPLED TO REFERENCE CELL FOR IMPROVED RELIABILITY
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01/25/2005
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10287363
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11/04/2002
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05/06/2004
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CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES
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03/22/2005
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10287612
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11/04/2002
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05/06/2004
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STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
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02/22/2005
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10288871
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Filing Dt:
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11/05/2002
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Title:
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METHOD OF ALTERNATING GROUNDED/FLOATING POLY LINES TO MONITOR SHORTS
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10291293
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Filing Dt:
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11/08/2002
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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METHOD OF FORMING FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10292121
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Filing Dt:
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11/12/2002
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Title:
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FABRICATION OF SHALLOW TRENCH ISOLATION STRUCTURES WITH ROUNDED CORNER AND SELF-ALIGNED GATE
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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10295738
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Filing Dt:
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11/15/2002
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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METHOD OF FABRICATING NITRIDATED TUNNEL OXIDE BARRIERS FOR FLASH MEMORY DEVICES HAVING STI AND LOCOS ISOLATION
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10298512
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Filing Dt:
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11/19/2002
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Publication #:
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Pub Dt:
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07/24/2003
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Title:
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NON-VOLATILE SEMICONDUCTOR MEMORY WITH A FUNCTION FOR PREVENTING UNAUTHORIZED READING
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10302672
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Filing Dt:
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11/22/2002
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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CASCODE AMPLIFIER CIRCUIT FOR PRODUCING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10304762
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Filing Dt:
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11/27/2002
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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SEMICONDUCTOR MEMORY APPARATUS
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10304863
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Filing Dt:
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11/27/2002
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Publication #:
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Pub Dt:
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02/12/2004
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Title:
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MEMORY DEVICE
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10305700
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Filing Dt:
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11/26/2002
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Title:
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METHOD AND SYSTEM FOR DEFINING A REDUNDANCY WINDOW AROUND A PARTICULAR COLUMN IN A MEMORY ARRAY
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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10305724
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Filing Dt:
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11/26/2002
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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LATERAL DOPED CHANNEL
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10305750
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Filing Dt:
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11/26/2002
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Title:
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METHOD OF PROTECTING A MEMORY ARRAY FROM CHARGE DAMAGE DURING FABRICATION
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10305756
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Filing Dt:
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11/26/2002
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Title:
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PROGRAM ALGORITHM INCLUDING SOFT ERASE FOR SONOS MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10305889
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Filing Dt:
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11/26/2002
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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MOCVD FORMATION OF CU2S
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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10306080
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Filing Dt:
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11/26/2002
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Title:
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MEMORY CIRCUIT FOR SUPPRESSING BIT LINE CURRENT LEAKAGE
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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10306252
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Filing Dt:
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11/27/2002
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Publication #:
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Pub Dt:
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09/02/2004
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Title:
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METHOD AND SYSTEM FOR ERASING A NITRIDE MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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10306382
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Filing Dt:
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11/27/2002
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Title:
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METHOD FOR PRODUCING A LOW DEFECT HOMOGENEOUS OXYNITRIDE
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10306529
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Filing Dt:
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11/27/2002
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Title:
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METHOD FOR FABRICATING NITRIDE MEMORY CELLS USING A FLOATING GATE FABRICATION PROCESS
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10306667
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Filing Dt:
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11/26/2002
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Title:
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METHOD OF DETERMINING CHARGE LOSS ACTIVATION ENERGY OF A MEMORY ARRAY
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10307189
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Filing Dt:
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11/29/2002
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Title:
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MEMORY WITH IMPROVED CHARGE-TRAPPING DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10307667
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Filing Dt:
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12/02/2002
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Title:
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SYSTEM FOR PROGRAMMING A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10307749
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Filing Dt:
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12/02/2002
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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PRE-CHARGE METHOD FOR READING A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10308518
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Filing Dt:
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12/03/2002
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Title:
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ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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10313444
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Filing Dt:
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12/05/2002
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Title:
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CIRCUIT FOR ACCURATE MEMORY READ OPERATIONS
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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10313454
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Filing Dt:
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12/05/2002
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Title:
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STRUCTURE AND METHOD FOR REDUCING CHARGE LOSS IN A MEMORY CELL
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10313494
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Filing Dt:
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12/05/2002
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Title:
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METHODS OF FORMING PASSIVE LAYERS IN ORGANIC MEMORY CELLS
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10313676
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Filing Dt:
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12/05/2002
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Title:
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EFFICIENT METHOD TO DETECT PROCESS INDUCED DEFECTS IN THE GATE STACK OF FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10314054
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Filing Dt:
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12/05/2002
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Title:
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IMPLANTATION FOR THE FORMATION OF CUX LAYER IN AN ORGANIC MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10314060
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Filing Dt:
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12/05/2002
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Title:
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METHOD OF FORMING COPPER SULFIDE FOR MEMORY CELL
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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10314591
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Filing Dt:
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12/09/2002
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Publication #:
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Pub Dt:
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06/10/2004
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Title:
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SELF ALIGNED MEMORY ELEMENT AND WORDLINE
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10314837
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Filing Dt:
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12/09/2002
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Title:
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SELECTIVE FORMATION OF TOP MEMORY ELECTRODE BY ELECTROLESS FORMATION OF CONDUCTIVE MATERIALS
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10315458
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Filing Dt:
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12/09/2002
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Title:
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DISCONTINUOUS NITRIDE STRUCTURE FOR NON-VOLATILE TRANSISTORS
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10315632
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Filing Dt:
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12/10/2002
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Title:
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FLASH MEMORY DEVICE HAVING FOUR-BIT CELLS
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10316569
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Filing Dt:
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12/10/2002
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Publication #:
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Pub Dt:
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06/10/2004
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Title:
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METHOD AND SYSTEM FOR REDUCING CONTACT DEFECTS USING NON CONVENTIONAL CONTACT FORMATION METHOD FOR SEMICONDUCTOR CELLS
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10320910
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Filing Dt:
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12/17/2002
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Title:
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DIFFERENTIALLY MIS-ALIGNED CONTACTS IN FLASH ARRAYS TO CALIBRATE FAILURE MODES
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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10331938
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Filing Dt:
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12/30/2002
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Title:
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TREATMENT OF DIELECTRIC MATERIAL TO ENHANCE ETCH RATE
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10338333
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Filing Dt:
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01/07/2003
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Title:
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SYSTEM AND METHOD FOR CHARGE RESTORATION IN A NON-VOLATILE MEMORY DEVICE
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