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Total properties:
19
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Patent #:
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Issue Dt:
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12/18/2007
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Application #:
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11207665
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Filing Dt:
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08/18/2005
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Publication #:
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Pub Dt:
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12/14/2006
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Title:
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ELECTRONIC DEVICE HAVING AN INTERFACE SUPPORTED TESTING MODE
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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11208099
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Filing Dt:
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08/18/2005
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Title:
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PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES
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Patent #:
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Issue Dt:
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07/17/2007
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Application #:
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11223286
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Filing Dt:
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09/09/2005
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Publication #:
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Pub Dt:
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07/13/2006
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Title:
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SHARED BOND PAD FOR TESTING A MEMORY WITHIN A PACKAGED SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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07/22/2008
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Application #:
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11258484
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Filing Dt:
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10/24/2005
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Publication #:
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Pub Dt:
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04/26/2007
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Title:
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COMPONENT TESTING AND RECOVERY
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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11304445
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Filing Dt:
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12/14/2005
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Publication #:
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Pub Dt:
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07/06/2006
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Title:
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INTEGRATED CIRCUIT TESTING MODULE
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Patent #:
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Issue Dt:
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05/06/2008
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Application #:
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11369878
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Filing Dt:
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03/06/2006
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Publication #:
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Pub Dt:
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07/19/2007
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Title:
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INTEGRATED CIRCUIT TESTING MODULE INCLUDING DATA COMPRESSION
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Patent #:
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Issue Dt:
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04/29/2008
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Application #:
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11370769
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Filing Dt:
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03/07/2006
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Title:
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INTEGRATED CIRCUIT TESTING MODULE INCLUDING DATA GENERATOR
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Patent #:
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Issue Dt:
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11/04/2008
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Application #:
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11370795
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Filing Dt:
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03/07/2006
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Title:
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INTEGRATED CIRCUIT TESTING MODULE INCLUDING ADDRESS GENERATOR
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Patent #:
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Issue Dt:
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12/18/2007
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Application #:
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11443872
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Filing Dt:
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05/30/2006
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Publication #:
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Pub Dt:
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10/19/2006
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Title:
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INTEGRATED CIRCUIT TESTING MODULE INCLUDING COMMAND DRIVER
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Patent #:
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Issue Dt:
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12/16/2008
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Application #:
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11472016
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Filing Dt:
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06/20/2006
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Publication #:
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Pub Dt:
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01/18/2007
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Title:
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SHARED MEMORY BUS ARCHITECTURE FOR SYSTEM WITH PROCESSOR AND MEMORY UNITS
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Patent #:
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Issue Dt:
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12/11/2007
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Application #:
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11479061
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Filing Dt:
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06/30/2006
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Publication #:
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Pub Dt:
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11/09/2006
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Title:
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INTEGRATED CIRCUIT TEST ARRAY INCLUDING TEST MODULE
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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11480234
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Filing Dt:
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06/30/2006
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Title:
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DELAY LOCK LOOP DELAY ADJUSTING METHOD AND APPARATUS
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Patent #:
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|
Issue Dt:
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08/17/2010
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Application #:
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11538799
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Filing Dt:
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10/04/2006
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Publication #:
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Pub Dt:
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05/17/2007
| | | | |
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Title:
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TESTING AND RECOVERY IN A MULTILAYER DEVICE
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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11552938
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Filing Dt:
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10/25/2006
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Publication #:
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Pub Dt:
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04/05/2007
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Title:
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INTEGRATED CIRCUIT TESTING MODULE INCLUDING SIGNAL SHAPING INTERFACE
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Patent #:
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Issue Dt:
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04/24/2012
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Application #:
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11552944
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Filing Dt:
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10/25/2006
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Publication #:
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Pub Dt:
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03/22/2007
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Title:
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INTEGRATED CIRCUIT TESTING MODULE CONFIGURED FOR SET-UP AND HOLD TIME TESTING
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Patent #:
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Issue Dt:
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09/22/2009
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Application #:
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11744815
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Filing Dt:
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05/04/2007
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Publication #:
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Pub Dt:
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11/15/2007
| | | | |
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Title:
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MEMORY DEVICE INCLUDING MULTIPLEXED INPUTS
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Patent #:
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Issue Dt:
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04/27/2010
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Application #:
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11853006
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Filing Dt:
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09/10/2007
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Publication #:
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Pub Dt:
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03/13/2008
| | | | |
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Title:
|
DELAY LOCK LOOP DELAY ADJUSTING METHOD AND APPARATUS
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|
|
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Patent #:
|
|
Issue Dt:
|
12/16/2008
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Application #:
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11906731
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Filing Dt:
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10/02/2007
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Publication #:
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Pub Dt:
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04/17/2008
| | | | |
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Title:
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MEMORY ACCESSING CIRCUIT SYSTEM
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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11981854
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Filing Dt:
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10/31/2007
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Publication #:
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Pub Dt:
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03/13/2008
| | | | |
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Title:
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ELECTRONIC DEVICE HAVING AN INTERFACE SUPPORTED TESTING MODE
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