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Patent Assignment Details
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Reel/Frame:020174/0342   Pages: 5
Recorded: 11/29/2007
Attorney Dkt #:AELU.G0001
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 16
1
Patent #:
Issue Dt:
04/10/2012
Application #:
10176495
Filing Dt:
06/21/2002
Title:
METHODS AND APPARATUS FOR CLOCK AND DATA RECOVERY USING TRANSMISSION LINES
2
Patent #:
Issue Dt:
09/07/2004
Application #:
10213484
Filing Dt:
08/06/2002
Title:
ACTIV SHUNT-PEAKED LOGIC GATES
3
Patent #:
Issue Dt:
02/28/2006
Application #:
10370833
Filing Dt:
02/21/2003
Title:
METHODS AND APPARATUS FOR INJECTING AN EXTERNAL CLOCK INTO A CIRCUIT
4
Patent #:
Issue Dt:
07/11/2006
Application #:
10615093
Filing Dt:
07/07/2003
Title:
TUNED CONTINUOUS TIME DELAY FIR EQUALIZER
5
Patent #:
Issue Dt:
03/07/2006
Application #:
10778635
Filing Dt:
02/13/2004
Title:
METHODS AND APPARATUS FOR IMPROVING LARGE SIGNAL PERFORMANCE FOR ACTIVE SHUNT-PEAKED CIRCUITS
6
Patent #:
Issue Dt:
05/12/2009
Application #:
11044478
Filing Dt:
01/27/2005
Title:
METHODS AND APPARATUS FOR CLOCK AND DATA RECOVERY USING A SINGLE SOURCE
7
Patent #:
Issue Dt:
10/07/2008
Application #:
11296786
Filing Dt:
12/07/2005
Title:
METHODS AND APPARATUS FOR FREQUENCY SYNTHESIS WITH FEEDBACK INTERPOLATION
8
Patent #:
Issue Dt:
01/29/2008
Application #:
11321412
Filing Dt:
12/29/2005
Title:
METHODS AND APPARATUS FOR GENERATING MULTIPLE CLOCKS USING FEEDBACK INTERPOLATION
9
Patent #:
Issue Dt:
02/08/2011
Application #:
11367253
Filing Dt:
03/02/2006
Title:
METHODS AND CIRCUITS FOR DRIVING LARGE OFF-CHIP LOADS
10
Patent #:
Issue Dt:
08/16/2011
Application #:
11756139
Filing Dt:
05/31/2007
Title:
LOW POWER SERIAL LINK
11
Patent #:
Issue Dt:
12/07/2010
Application #:
11781712
Filing Dt:
07/23/2007
Title:
PROGRAMMABLE DELAY CLOCK BUFFER
12
Patent #:
Issue Dt:
12/21/2010
Application #:
11844836
Filing Dt:
08/24/2007
Title:
METHOD AND APPARATUS FOR SHAPING ELECTRONIC PULSES
13
Patent #:
Issue Dt:
10/14/2008
Application #:
11861690
Filing Dt:
09/26/2007
Publication #:
Pub Dt:
02/28/2008
Title:
METHODS AND APPARATUS FOR MINIMIZING JITTER IN A CLOCK SYNTHESIS CIRCUIT THAT USES FEEDBACK INTERPOLATION
14
Patent #:
Issue Dt:
03/16/2010
Application #:
11869595
Filing Dt:
10/09/2007
Title:
DIGITAL LINEAR VOLTAGE REGULATOR
15
Patent #:
Issue Dt:
01/24/2012
Application #:
11930978
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
02/28/2008
Title:
METHODS AND APPARATUS FOR CLOCK AND DATA RECOVERY USING TRANSMISSION LINES
16
Patent #:
Issue Dt:
10/28/2008
Application #:
11938164
Filing Dt:
11/09/2007
Title:
METHODS AND APPARATUS TO INCREASE THE RESOLUTION OF A CLOCK SYNTHESIS CIRCUIT THAT USES FEEDBACK INTERPOLATION
Assignor
1
Exec Dt:
11/29/2007
Assignee
1
1875 CHARLESTON RD.
MOUNTAIN VIEW, CALIFORNIA 94043
Correspondence name and address
JOHN STATTLER
60 SOUTH MARKET STREET SUITE 480
SAN JOSE, CA 95113

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