Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 024909/0343 | |
| Pages: | 24 |
| | Recorded: | 08/30/2010 | | |
| Attorney Dkt #: | ALGOTOCHIP1,1C,4,5,7 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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07/17/2012
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Application #:
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12835603
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Filing Dt:
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07/13/2010
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Publication #:
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Pub Dt:
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01/19/2012
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Title:
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AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION
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Patent #:
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Issue Dt:
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02/05/2013
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Application #:
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12835621
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Filing Dt:
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07/13/2010
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Publication #:
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Pub Dt:
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01/19/2012
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Title:
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AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION
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Patent #:
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Issue Dt:
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11/19/2013
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Application #:
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12835628
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Filing Dt:
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07/13/2010
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Publication #:
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Pub Dt:
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01/19/2012
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Title:
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APPLICATION DRIVEN POWER GATING
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Patent #:
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Issue Dt:
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07/09/2013
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Application #:
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12835631
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Filing Dt:
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07/13/2010
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Publication #:
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Pub Dt:
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01/19/2012
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Title:
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SYSTEM, ARCHITECTURE AND MICRO-ARCHITECTURE (SAMA) REPRESENTATION OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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05/22/2012
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Application #:
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12835640
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Filing Dt:
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07/13/2010
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Publication #:
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Pub Dt:
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01/19/2012
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Title:
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ARCHITECTURAL LEVEL POWER-AWARE OPTIMIZATION AND RISK MITIGATION
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Assignee
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| 530 LAKESIDE DR. SUITE #260 |
| SUNNYVALE, CALIFORNIA 94085 |
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Correspondence name and address
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BAO TRAN, TRAN & ASSOCIATES
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PO BOX 68
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SARATOGA, CA 95071
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