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Patent Assignment Details
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Reel/Frame:033484/0344   Pages: 110
Recorded: 08/07/2014
Conveyance: RELEASE OF SECURITY INTEREST
Total properties: 1360
Page 13 of 14
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1
Patent #:
Issue Dt:
01/28/2014
Application #:
12619355
Filing Dt:
11/16/2009
Publication #:
Pub Dt:
03/11/2010
Title:
METHOD AND SYSTEM FOR PACKET PROCESSING
2
Patent #:
Issue Dt:
07/19/2011
Application #:
12620749
Filing Dt:
11/18/2009
Publication #:
Pub Dt:
03/18/2010
Title:
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
3
Patent #:
Issue Dt:
07/12/2011
Application #:
12621983
Filing Dt:
11/19/2009
Publication #:
Pub Dt:
03/11/2010
Title:
BIAS GENERATOR PROVIDING FOR LOW POWER, SELF-BIASED DELAY ELEMENT AND DELAY LINE
4
Patent #:
Issue Dt:
10/19/2010
Application #:
12623899
Filing Dt:
11/23/2009
Publication #:
Pub Dt:
06/03/2010
Title:
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS
5
Patent #:
Issue Dt:
10/28/2014
Application #:
12627574
Filing Dt:
11/30/2009
Publication #:
Pub Dt:
06/03/2010
Title:
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
6
Patent #:
Issue Dt:
03/17/2015
Application #:
12627702
Filing Dt:
11/30/2009
Publication #:
Pub Dt:
06/03/2010
Title:
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
7
Patent #:
Issue Dt:
10/16/2012
Application #:
12627804
Filing Dt:
11/30/2009
Publication #:
Pub Dt:
06/03/2010
Title:
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
8
Patent #:
Issue Dt:
06/28/2011
Application #:
12633071
Filing Dt:
12/08/2009
Publication #:
Pub Dt:
06/17/2010
Title:
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
9
Patent #:
Issue Dt:
10/25/2011
Application #:
12635280
Filing Dt:
12/10/2009
Publication #:
Pub Dt:
07/08/2010
Title:
NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION
10
Patent #:
Issue Dt:
02/22/2011
Application #:
12638309
Filing Dt:
12/15/2009
Publication #:
Pub Dt:
06/24/2010
Title:
DELAY LOCKED LOOP CIRCUIT
11
Patent #:
Issue Dt:
07/10/2012
Application #:
12639531
Filing Dt:
12/16/2009
Publication #:
Pub Dt:
05/06/2010
Title:
INITIALIZATION CIRCUIT FOR DELAY LOCKED LOOP
12
Patent #:
Issue Dt:
06/05/2012
Application #:
12640388
Filing Dt:
12/17/2009
Publication #:
Pub Dt:
06/24/2010
Title:
SEMICONDUCTOR DEVICE WITH MAIN MEMORY UNIT AND AUXILIARY MEMORY UNIT REQUIRING PRESET OPERATION
13
Patent #:
Issue Dt:
02/15/2011
Application #:
12651707
Filing Dt:
01/04/2010
Publication #:
Pub Dt:
04/22/2010
Title:
MEMORY SYSTEM HAVING INCORRUPTED STROBE SIGNALS
14
Patent #:
Issue Dt:
04/02/2013
Application #:
12652897
Filing Dt:
01/06/2010
Publication #:
Pub Dt:
07/08/2010
Title:
CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS
15
Patent #:
Issue Dt:
06/24/2014
Application #:
12683731
Filing Dt:
01/07/2010
Publication #:
Pub Dt:
04/29/2010
Title:
TELEPHONE OUTLET WITH PACKET TELEPHONY ADAPTER, AND A NETWORK USING SAME
16
Patent #:
Issue Dt:
06/26/2012
Application #:
12684026
Filing Dt:
01/07/2010
Publication #:
Pub Dt:
05/13/2010
Title:
A DOUBLE DATA RATE CONVERTER CIRCUIT INCLUDES A DELAY LOCKED LOOP FOR PROVIDING THE PLURALITY OF CLOCK PHASE SIGNALS
17
Patent #:
Issue Dt:
11/22/2011
Application #:
12685365
Filing Dt:
01/11/2010
Publication #:
Pub Dt:
08/12/2010
Title:
TERMINATION CIRCUIT FOR ON-DIE TERMINATION
18
Patent #:
Issue Dt:
06/25/2013
Application #:
12685694
Filing Dt:
01/12/2010
Publication #:
Pub Dt:
07/29/2010
Title:
TELEPHONE OUTLET WITH PACKET TELEPHONY ADAPTOR, AND A NETWORK USING SAME
19
Patent #:
Issue Dt:
01/04/2011
Application #:
12687541
Filing Dt:
01/14/2010
Publication #:
Pub Dt:
05/13/2010
Title:
TIMING VERNIER USING A DELAY LOCKED LOOP
20
Patent #:
Issue Dt:
12/04/2012
Application #:
12691794
Filing Dt:
01/22/2010
Publication #:
Pub Dt:
05/13/2010
Title:
VOLTAGE LEVEL SHIFTER AND BUFFER USING SAME
21
Patent #:
Issue Dt:
03/22/2011
Application #:
12698585
Filing Dt:
02/02/2010
Publication #:
Pub Dt:
06/03/2010
Title:
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
22
Patent #:
Issue Dt:
03/27/2012
Application #:
12699627
Filing Dt:
02/03/2010
Publication #:
Pub Dt:
08/12/2010
Title:
MEMORY WITH DATA CONTROL
23
Patent #:
Issue Dt:
01/11/2011
Application #:
12700370
Filing Dt:
02/04/2010
Publication #:
Pub Dt:
06/10/2010
Title:
PHASE-LOCKED LOOP CIRCUITRY USING CHARGE PUMPS WITH CURRENT MIRROR CIRCUITRY
24
Patent #:
Issue Dt:
03/04/2014
Application #:
12701122
Filing Dt:
02/05/2010
Publication #:
Pub Dt:
02/17/2011
Title:
PACKAGE-LEVEL INTEGRATED CIRCUIT CONNECTION WITHOUT TOP METAL PADS OR BONDING WIRE
25
Patent #:
Issue Dt:
10/30/2012
Application #:
12705040
Filing Dt:
02/12/2010
Publication #:
Pub Dt:
06/10/2010
Title:
DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS WITH TEMPERATURE COMPENSATED SELF-REFRESH
26
Patent #:
Issue Dt:
12/13/2011
Application #:
12705345
Filing Dt:
02/12/2010
Publication #:
Pub Dt:
09/16/2010
Title:
SRAM LEAKAGE REDUCTION CIRCUIT
27
Patent #:
Issue Dt:
07/24/2012
Application #:
12709198
Filing Dt:
02/19/2010
Title:
BLOCK PROGRAMMABLE PRIORITY ENCODER IN A CAM
28
Patent #:
Issue Dt:
02/22/2011
Application #:
12714670
Filing Dt:
03/01/2010
Publication #:
Pub Dt:
08/26/2010
Title:
CHARGE PUMP FOR PLL/DLL
29
Patent #:
Issue Dt:
10/25/2011
Application #:
12715641
Filing Dt:
03/02/2010
Publication #:
Pub Dt:
06/24/2010
Title:
APPARATUS AND METHOD FOR SELF-REFRESHING DYNAMIC RANDOM ACCESS MEMORY CELLS
30
Patent #:
Issue Dt:
02/28/2012
Application #:
12718300
Filing Dt:
03/05/2010
Publication #:
Pub Dt:
09/02/2010
Title:
METHOD AND APPARATUS FOR PROVIDING A PACKET BUFFER RANDOM ACCESS MEMORY
31
Patent #:
Issue Dt:
09/20/2011
Application #:
12719413
Filing Dt:
03/08/2010
Publication #:
Pub Dt:
06/24/2010
Title:
FLASH MEMORY PROGRAM INHIBIT SCHEME
32
Patent #:
Issue Dt:
11/15/2011
Application #:
12724952
Filing Dt:
03/16/2010
Publication #:
Pub Dt:
07/08/2010
Title:
SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION
33
Patent #:
Issue Dt:
01/29/2013
Application #:
12727375
Filing Dt:
03/19/2010
Publication #:
Pub Dt:
09/30/2010
Title:
TELEPHONE OUTLET FOR IMPLEMENTING A LOCAL AREA NETWORK OVER TELEPHONE LINES AND A LOCAL AREA NETWORK USING SUCH OUTLETS
34
Patent #:
Issue Dt:
08/16/2011
Application #:
12732745
Filing Dt:
03/26/2010
Publication #:
Pub Dt:
07/22/2010
Title:
METHOD AND SYSTEM FOR ACCESSING A FLASH MEMORY DEVICE
35
Patent #:
Issue Dt:
10/11/2011
Application #:
12750119
Filing Dt:
03/30/2010
Publication #:
Pub Dt:
07/22/2010
Title:
SIMPLIFIED BIAS CIRCUITRY FOR DIFFERENTIAL BUFFER STAGE WITH SYMMETRIC LOADS
36
Patent #:
Issue Dt:
10/28/2014
Application #:
12753271
Filing Dt:
04/02/2010
Publication #:
Pub Dt:
10/07/2010
Title:
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
37
Patent #:
Issue Dt:
10/21/2014
Application #:
12753458
Filing Dt:
04/02/2010
Publication #:
Pub Dt:
10/07/2010
Title:
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
38
Patent #:
Issue Dt:
05/17/2011
Application #:
12757406
Filing Dt:
04/09/2010
Publication #:
Pub Dt:
08/05/2010
Title:
INDEPENDENT LINK AND BANK SELECTION
39
Patent #:
Issue Dt:
03/19/2013
Application #:
12757540
Filing Dt:
04/09/2010
Publication #:
Pub Dt:
03/03/2011
Title:
USING INTERRUPTED THROUGH-SILICON-VIAS IN INTEGRATED CIRCUITS ADAPTED FOR STACKING
40
Patent #:
Issue Dt:
10/09/2012
Application #:
12764607
Filing Dt:
04/21/2010
Publication #:
Pub Dt:
08/12/2010
Title:
FLOW-FILL SPACER STRUCTURES FOR FLAT PANEL DISPLAY DEVICE
41
Patent #:
Issue Dt:
08/06/2013
Application #:
12770376
Filing Dt:
04/29/2010
Publication #:
Pub Dt:
11/25/2010
Title:
CONFIGURABLE MODULE AND MEMORY SUBSYSTEM
42
Patent #:
Issue Dt:
12/10/2013
Application #:
12773340
Filing Dt:
05/04/2010
Publication #:
Pub Dt:
04/21/2011
Title:
RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES
43
Patent #:
Issue Dt:
12/13/2011
Application #:
12773531
Filing Dt:
05/04/2010
Publication #:
Pub Dt:
08/26/2010
Title:
SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE
44
Patent #:
Issue Dt:
08/09/2011
Application #:
12775696
Filing Dt:
05/07/2010
Publication #:
Pub Dt:
09/30/2010
Title:
METHOD AND APPARATUS FOR REDUCING POOL STARVATION IN A SHARED MEMORY SWITCH
45
Patent #:
Issue Dt:
05/31/2011
Application #:
12782047
Filing Dt:
05/18/2010
Publication #:
Pub Dt:
09/09/2010
Title:
MULTIPLE BIT PER CELL NON VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME
46
Patent #:
Issue Dt:
11/12/2013
Application #:
12782911
Filing Dt:
05/19/2010
Publication #:
Pub Dt:
09/29/2011
Title:
MEMORY SYSTEM HAVING A PLURALITY OF SERIALLY CONNECTED DEVICES
47
Patent #:
Issue Dt:
10/09/2012
Application #:
12784157
Filing Dt:
05/20/2010
Publication #:
Pub Dt:
09/09/2010
Title:
FREQUENCY-DOUBLING DELAY LOCKED LOOP
48
Patent #:
Issue Dt:
07/24/2012
Application #:
12784238
Filing Dt:
05/20/2010
Publication #:
Pub Dt:
10/21/2010
Title:
APPARATUS AND METHOD FOR COMMUNICATING WITH SEMICONDUCTOR DEVICES OF A SERIAL INTERCONNECTION
49
Patent #:
Issue Dt:
10/25/2011
Application #:
12785051
Filing Dt:
05/21/2010
Publication #:
Pub Dt:
09/16/2010
Title:
HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY
50
Patent #:
Issue Dt:
09/23/2014
Application #:
12785099
Filing Dt:
05/21/2010
Publication #:
Pub Dt:
09/09/2010
Title:
PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY
51
Patent #:
Issue Dt:
09/10/2013
Application #:
12812500
Filing Dt:
07/12/2010
Publication #:
Pub Dt:
12/02/2010
Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
52
Patent #:
Issue Dt:
12/31/2013
Application #:
12816130
Filing Dt:
06/15/2010
Publication #:
Pub Dt:
04/07/2011
Title:
SYSTEM AND METHOD PROVIDING INTEROPERABILITY BETWEEN CELLULAR AND OTHER WIRELESS SYSTEMS
53
Patent #:
Issue Dt:
11/12/2013
Application #:
12819467
Filing Dt:
06/21/2010
Title:
SINGLE CHIP FRAME BUFFER AND GRAPHICS ACCELERATOR
54
Patent #:
Issue Dt:
08/06/2013
Application #:
12823472
Filing Dt:
06/25/2010
Publication #:
Pub Dt:
12/30/2010
Title:
BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN
55
Patent #:
Issue Dt:
10/23/2012
Application #:
12827718
Filing Dt:
06/30/2010
Publication #:
Pub Dt:
10/21/2010
Title:
METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE
56
Patent #:
Issue Dt:
03/15/2011
Application #:
12832121
Filing Dt:
07/08/2010
Publication #:
Pub Dt:
10/28/2010
Title:
APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA
57
Patent #:
Issue Dt:
04/17/2012
Application #:
12851884
Filing Dt:
08/06/2010
Publication #:
Pub Dt:
12/02/2010
Title:
DATA FLOW CONTROL IN MULTIPLE INDEPENDENT PORT
58
Patent #:
Issue Dt:
04/12/2011
Application #:
12852082
Filing Dt:
08/06/2010
Publication #:
Pub Dt:
11/25/2010
Title:
METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME
59
Patent #:
NONE
Issue Dt:
Application #:
12855171
Filing Dt:
08/12/2010
Publication #:
Pub Dt:
12/23/2010
Title:
FLASH MEMORY SYSTEM CONTROL SCHEME
60
Patent #:
Issue Dt:
05/22/2012
Application #:
12862497
Filing Dt:
08/24/2010
Publication #:
Pub Dt:
12/23/2010
Title:
PORT PACKET QUEUING
61
Patent #:
Issue Dt:
06/07/2011
Application #:
12878601
Filing Dt:
09/09/2010
Publication #:
Pub Dt:
12/30/2010
Title:
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS
62
Patent #:
Issue Dt:
12/02/2014
Application #:
12879543
Filing Dt:
09/10/2010
Publication #:
Pub Dt:
12/30/2010
Title:
APPARATUS AND METHOD FOR CAPTURING SERIAL INPUT DATA
63
Patent #:
Issue Dt:
10/16/2012
Application #:
12879566
Filing Dt:
09/10/2010
Publication #:
Pub Dt:
01/20/2011
Title:
NON-VOLATILE MEMORY BANK AND PAGE BUFFER THEREFOR
64
Patent #:
Issue Dt:
06/12/2012
Application #:
12882931
Filing Dt:
09/15/2010
Publication #:
Pub Dt:
01/06/2011
Title:
MEMORY WITH OUTPUT CONTROL
65
Patent #:
Issue Dt:
01/24/2012
Application #:
12884939
Filing Dt:
09/17/2010
Publication #:
Pub Dt:
01/13/2011
Title:
FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME
66
Patent #:
Issue Dt:
08/09/2011
Application #:
12888034
Filing Dt:
09/22/2010
Publication #:
Pub Dt:
03/24/2011
Title:
NON-VOLATILE SEMICONDUCTOR MEMORY WITH PAGE ERASE
67
Patent #:
Issue Dt:
06/05/2012
Application #:
12892215
Filing Dt:
09/28/2010
Publication #:
Pub Dt:
01/20/2011
Title:
APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION
68
Patent #:
Issue Dt:
03/19/2013
Application #:
12900395
Filing Dt:
10/07/2010
Publication #:
Pub Dt:
01/27/2011
Title:
CONGESTION MANAGEMENT IN A NETWORK
69
Patent #:
Issue Dt:
11/22/2011
Application #:
12903271
Filing Dt:
10/13/2010
Publication #:
Pub Dt:
02/10/2011
Title:
POWER SUPPLIES IN FLASH MEMORY DEVICES AND SYSTEMS
70
Patent #:
Issue Dt:
04/23/2013
Application #:
12907210
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
04/19/2012
Title:
ERROR DETECTION AND CORRECTION CODES FOR CHANNELS AND MEMORIES WITH INCOMPLETE ERROR CHARACTERISTICS
71
Patent #:
Issue Dt:
12/31/2013
Application #:
12912235
Filing Dt:
10/26/2010
Publication #:
Pub Dt:
02/17/2011
Title:
COMMUNICATION SYSTEM AND METHOD OVER LOCAL AREA NETWORK WIRING
72
Patent #:
Issue Dt:
10/11/2011
Application #:
12915796
Filing Dt:
10/29/2010
Publication #:
Pub Dt:
02/24/2011
Title:
DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS
73
Patent #:
Issue Dt:
05/14/2013
Application #:
12945280
Filing Dt:
11/12/2010
Publication #:
Pub Dt:
03/10/2011
Title:
METHODS AND SYSTEMS FOR FAILURE ISOLATION AND DATA RECOVERY IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES
74
Patent #:
Issue Dt:
04/29/2014
Application #:
12948186
Filing Dt:
11/17/2010
Publication #:
Pub Dt:
03/10/2011
Title:
METHODS AND APPARATUS FOR CLOCK SIGNAL SYNCHRONIZATION IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES
75
Patent #:
Issue Dt:
09/06/2011
Application #:
12950305
Filing Dt:
11/19/2010
Publication #:
Pub Dt:
03/17/2011
Title:
TIMING VERNIER USING A DELAY LOCKED LOOP
76
Patent #:
Issue Dt:
04/16/2013
Application #:
12958287
Filing Dt:
12/01/2010
Publication #:
Pub Dt:
03/24/2011
Title:
SEMICONDUCTOR DEVICE HAVING METAL LINES WITH SLITS
77
Patent #:
Issue Dt:
02/24/2015
Application #:
12967918
Filing Dt:
12/14/2010
Publication #:
Pub Dt:
08/25/2011
Title:
SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE
78
Patent #:
Issue Dt:
10/23/2012
Application #:
12982599
Filing Dt:
12/30/2010
Publication #:
Pub Dt:
04/28/2011
Title:
MEMORY DEVICE AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY
79
Patent #:
Issue Dt:
02/19/2013
Application #:
12984163
Filing Dt:
01/04/2011
Publication #:
Pub Dt:
04/28/2011
Title:
PROCESS, VOLTAGE, TEMPERATURE INDEPENDENT SWITCHED DELAY COMPENSATION SCHEME
80
Patent #:
Issue Dt:
01/10/2012
Application #:
12984834
Filing Dt:
01/05/2011
Publication #:
Pub Dt:
04/28/2011
Title:
MODULAR OUTLET
81
Patent #:
Issue Dt:
03/26/2013
Application #:
12984987
Filing Dt:
01/05/2011
Publication #:
Pub Dt:
04/28/2011
Title:
SINGLE-STROBE OPERATION OF MEMORY DEVICES
82
Patent #:
NONE
Issue Dt:
Application #:
12986539
Filing Dt:
01/07/2011
Publication #:
Pub Dt:
04/28/2011
Title:
OUTLET WITH ANALOG SIGNAL ADAPTER, A METHOD FOR USE THEREOF AND A NETWORK USING SAID OUTLET
83
Patent #:
Issue Dt:
11/01/2011
Application #:
12986646
Filing Dt:
01/07/2011
Publication #:
Pub Dt:
05/05/2011
Title:
CHARGE PUMP FOR PLL/DLL
84
Patent #:
Issue Dt:
06/26/2012
Application #:
12986684
Filing Dt:
01/07/2011
Publication #:
Pub Dt:
05/12/2011
Title:
DELAY LOCKED LOOP CIRCUIT
85
Patent #:
Issue Dt:
02/12/2013
Application #:
13004461
Filing Dt:
01/11/2011
Publication #:
Pub Dt:
05/05/2011
Title:
DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS
86
Patent #:
Issue Dt:
07/03/2012
Application #:
13005231
Filing Dt:
01/12/2011
Publication #:
Pub Dt:
05/12/2011
Title:
BARRIER-METAL-FREE COPPER CAMASCENCE TECHNOLOGY USING ATOMIC HYDROGEN ENHANCED REFLOW
87
Patent #:
Issue Dt:
12/25/2012
Application #:
13005774
Filing Dt:
01/13/2011
Publication #:
Pub Dt:
05/12/2011
Title:
STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE
88
Patent #:
Issue Dt:
04/30/2013
Application #:
13006005
Filing Dt:
01/13/2011
Publication #:
Pub Dt:
05/12/2011
Title:
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
89
Patent #:
Issue Dt:
10/29/2013
Application #:
13008522
Filing Dt:
01/18/2011
Publication #:
Pub Dt:
10/13/2011
Title:
MEMORY PROGRAMMING USING VARIABLE DATA WIDTH
90
Patent #:
Issue Dt:
06/11/2013
Application #:
13012754
Filing Dt:
01/24/2011
Publication #:
Pub Dt:
12/01/2011
Title:
HIGH-SPEED INTERFACE FOR DAISY-CHAINED DEVICES
91
Patent #:
NONE
Issue Dt:
Application #:
13016396
Filing Dt:
01/28/2011
Publication #:
Pub Dt:
06/02/2011
Title:
MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM
92
Patent #:
Issue Dt:
10/02/2012
Application #:
13019100
Filing Dt:
02/01/2011
Publication #:
Pub Dt:
05/26/2011
Title:
PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES
93
Patent #:
Issue Dt:
11/15/2011
Application #:
13022166
Filing Dt:
02/07/2011
Publication #:
Pub Dt:
06/02/2011
Title:
APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA
94
Patent #:
NONE
Issue Dt:
Application #:
13023838
Filing Dt:
02/09/2011
Publication #:
Pub Dt:
10/20/2011
Title:
STATUS INDICATION IN A SYSTEM HAVING A PLURALITY OF MEMORY DEVICES
95
Patent #:
Issue Dt:
12/20/2011
Application #:
13030785
Filing Dt:
02/18/2011
Publication #:
Pub Dt:
06/16/2011
Title:
CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
96
Patent #:
Issue Dt:
04/03/2012
Application #:
13032175
Filing Dt:
02/22/2011
Publication #:
Pub Dt:
08/25/2011
Title:
CIRCUIT FOR CLAMPING CURRENT IN A CHARGE PUMP
97
Patent #:
Issue Dt:
03/05/2013
Application #:
13033294
Filing Dt:
02/23/2011
Publication #:
Pub Dt:
06/23/2011
Title:
DATA CHANNEL TEST APPARATUS AND METHOD THEREOF
98
Patent #:
Issue Dt:
03/27/2012
Application #:
13035580
Filing Dt:
02/25/2011
Publication #:
Pub Dt:
09/29/2011
Title:
NON-VOLATILE MEMORY DEVICES AND CONTROL AND OPERATION THEREOF
99
Patent #:
NONE
Issue Dt:
Application #:
13037113
Filing Dt:
02/28/2011
Publication #:
Pub Dt:
09/01/2011
Title:
SEQUENTIAL PULSE DEPOSITION
100
Patent #:
Issue Dt:
08/04/2015
Application #:
13038461
Filing Dt:
03/02/2011
Publication #:
Pub Dt:
09/22/2011
Title:
COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION
Assignor
1
Exec Dt:
06/11/2014
Assignees
1
11 HINES ROAD
SUITE 203
OTTAWA, ONTARIO, CANADA K2K2X1
2
44 CHIPMAN HILL
SUITE 1000
SAINT JOHN, NB, CANADA E2L 2A9
3
570 QUEEN STREET
SUITE 600
FREDERICTON, NB, CANADA E3B 6Z6
Correspondence name and address
CONVERSANT INTELLECTUAL PROPERTY MGMT
5601 GRANITE PARKWAY
SUITE 1300
PLANO, TX 75024

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