|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
10888838
|
Filing Dt:
|
07/12/2004
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
Title:
|
METHOD OF FORMING A METAL OXIDE FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10889194
|
Filing Dt:
|
07/12/2004
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
REDUNDANCY CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE HAVING A MULTIBLOCK STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10889203
|
Filing Dt:
|
07/12/2004
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
Title:
|
BARRIER-METAL-FREE COPPER DAMASCENE TECHNOLOGY USING ATOMIC HYDROGEN ENHANCED REFLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
10890199
|
Filing Dt:
|
07/14/2004
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
Title:
|
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
10909301
|
Filing Dt:
|
08/03/2004
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
TELEPHONE COMMUNICATION SYSTEM OVER A SINGLE TELEPHONE LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10912768
|
Filing Dt:
|
08/05/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
CONTENT ADDRESSABLE MEMORY ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10913555
|
Filing Dt:
|
08/06/2004
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
CHEMICAL TREATMENT OF SEMICONDUCTOR SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10914888
|
Filing Dt:
|
08/09/2004
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
DIELECTRIC MATERIAL FORMING METHODS AND ENHANCED DIELECTRIC MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10917494
|
Filing Dt:
|
08/13/2004
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10919370
|
Filing Dt:
|
08/17/2004
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
INPUT SIGNAL RECEIVING DEVICE OF SEMICONDUCTOR MEMORY UNIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
10919491
|
Filing Dt:
|
08/17/2004
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
HIGH BANDWIDTH MEMORY INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
10921491
|
Filing Dt:
|
08/19/2004
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR TRAVERSING A MULTIPLEXED DATA PACKET STREAM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2007
|
Application #:
|
10931396
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
STRUCTURES AND METHODS FOR ENHANCING CAPACITORS IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10931592
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
SYSTEM AND METHOD FOR SELECTIVELY INCREASING SURFACE TEMPERATURE OF AN OBJECT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10931714
|
Filing Dt:
|
09/01/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
ANTIFUSE STRUCTURE AND METHOD OF USE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10932503
|
Filing Dt:
|
09/02/2004
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
Title:
|
CAPACITOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10932771
|
Filing Dt:
|
09/02/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
REDUCING ASYMMETRICALLY DEPOSITED FILM INDUCED REGISTRATION ERROR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10937519
|
Filing Dt:
|
09/09/2004
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
PACKET ADDRESSING PROGRAMMABLE DUAL PORT MEMORY DEVICES AND RELATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10940231
|
Filing Dt:
|
09/14/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
TEMPERATURE-DEPENDENT DRAM SELF-REFRESH CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10940808
|
Filing Dt:
|
08/24/2004
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
MULTI-LEVEL HIGH VOLTAGE GENERATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10942367
|
Filing Dt:
|
09/15/2004
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING A POCKET LINE AND METHODS OF FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10945535
|
Filing Dt:
|
09/20/2004
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
PROCESS FOR THE FABRICATION OF OXIDE FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10946016
|
Filing Dt:
|
09/22/2004
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10965513
|
Filing Dt:
|
10/14/2004
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
APPARATUS FOR THE AUTOMATED TESTING, CALIBRATION AND CHARACTERIZATION OF TEST ADAPTERS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10972324
|
Filing Dt:
|
10/26/2004
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
SYNCHRONOUS DRAM WITH SELECTABLE INTERNAL PREFETCH SIZE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
10975020
|
Filing Dt:
|
10/28/2004
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
Title:
|
NETWORK FOR TELEPHONY AND DATA COMMUNICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10976626
|
Filing Dt:
|
10/29/2004
|
Publication #:
|
|
Pub Dt:
|
07/07/2005
| | | | |
Title:
|
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SCALABLE TWO TRANSISTOR MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10986299
|
Filing Dt:
|
11/12/2004
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
10988565
|
Filing Dt:
|
11/16/2004
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
Title:
|
TELEPHONE OUTLET WITH PACKET TELEPHONY ADAPTOR, AND A NETWORK USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10991042
|
Filing Dt:
|
11/16/2004
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER WITH INCREASED SPEED
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10992963
|
Filing Dt:
|
11/18/2004
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH CYLINDRICAL STORAGE ELECTRODE AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10996739
|
Filing Dt:
|
11/24/2004
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
10998015
|
Filing Dt:
|
11/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
11001057
|
Filing Dt:
|
12/02/2004
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
TELEPHONE OUTLET WITH PACKET TELEPHONY ADAPTER, AND A NETWORK USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
11002706
|
Filing Dt:
|
12/03/2004
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
11004806
|
Filing Dt:
|
12/07/2004
|
Publication #:
|
|
Pub Dt:
|
03/09/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
11006582
|
Filing Dt:
|
12/08/2004
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
Title:
|
ADAPTER FOR MOUNTING A FACEPLATE OF A FIRST STYLE ON TO AN ELECTRICAL OUTLET CAVITY OF A SECOND STYLE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
11008672
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
08/11/2005
| | | | |
Title:
|
VOLTAGE REGULATING CIRCUIT AND METHOD OF REGULATING VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
11009534
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
HIGH OUTPUT IMPEDANCE CHARGE PUMP FOR PLL/DLL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
11015421
|
Filing Dt:
|
12/20/2004
|
Publication #:
|
|
Pub Dt:
|
06/30/2005
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH EFFICIENT MULTIPLEXING OF I/O PAD IN MULTI-CHIP PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11020193
|
Filing Dt:
|
12/27/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
NETWORK FOR TELEPHONY AND DATA COMMUNICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11020277
|
Filing Dt:
|
12/27/2004
|
Publication #:
|
|
Pub Dt:
|
06/30/2005
| | | | |
Title:
|
METHOD OF FORMING AN INTERCONNECTION LINE IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11025765
|
Filing Dt:
|
12/28/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
HIGH VOLTAGE GENERATOR CIRCUIT WITH RIPPLE STABILIZATION FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
11025800
|
Filing Dt:
|
12/28/2004
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE FOR LOW POWER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11026014
|
Filing Dt:
|
01/03/2005
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
TELEPHONE COMMUNICATION SYSTEM OVER A SINGLE TELEPHONE LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2005
|
Application #:
|
11026970
|
Filing Dt:
|
12/30/2004
|
Title:
|
DELAY LOCKED LOOP AND LOCKING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
11032381
|
Filing Dt:
|
01/10/2005
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
MAIN AMPLIFIER AND SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
11037365
|
Filing Dt:
|
01/19/2005
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
TIMING VERNIER USING A DELAY LOCKED LOOP
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2006
|
Application #:
|
11038602
|
Filing Dt:
|
01/18/2005
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
GAPPED-PLATE CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
11041687
|
Filing Dt:
|
01/20/2005
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
Title:
|
LOW LEAKAGE AND DATA RETENTION CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
11048370
|
Filing Dt:
|
01/31/2005
|
Publication #:
|
|
Pub Dt:
|
11/24/2005
| | | | |
Title:
|
DYNAMIC TRAFFIC REARRANGEMENT AND RESTORATION FOR MPLS NETWORKS WITH DIFFERENTIATED SERVICES CAPABILITIES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
|
Application #:
|
11050644
|
Filing Dt:
|
02/03/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR INITIALIZING A DELAY LOCKED LOOP
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
11079216
|
Filing Dt:
|
03/15/2005
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
Title:
|
CAPACITOR OF AN INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2009
|
Application #:
|
11091371
|
Filing Dt:
|
03/29/2005
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
DEVICE, METHOD AND SYSTEM FOR ESTIMATING THE TERMINATION TO A WIRED TRANSMISSION-LINE BASED ON DETERMINATION OF CHARACTERISTIC IMPEDANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
11100453
|
Filing Dt:
|
04/07/2005
|
Publication #:
|
|
Pub Dt:
|
09/08/2005
| | | | |
Title:
|
SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2009
|
Application #:
|
11100461
|
Filing Dt:
|
04/07/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
NETWORK FOR TELEPHONY AND DATA COMMUNICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
11101413
|
Filing Dt:
|
04/08/2005
|
Publication #:
|
|
Pub Dt:
|
08/18/2005
| | | | |
Title:
|
HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
11107958
|
Filing Dt:
|
04/18/2005
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR ACCELERATING RETRIEVAL OF DATA FROM A MEMORY SYSTEM WITH CACHE BY REDUCING LATENCY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11108651
|
Filing Dt:
|
04/11/2005
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
Title:
|
METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
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11118229
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Filing Dt:
|
04/28/2005
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Publication #:
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|
Pub Dt:
|
02/09/2006
| | | | |
Title:
|
FIXED OFFSET DIGITAL-TO-ANALOG CONVERSION DEVICE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
11121075
|
Filing Dt:
|
05/04/2005
|
Publication #:
|
|
Pub Dt:
|
11/17/2005
| | | | |
Title:
|
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
11122718
|
Filing Dt:
|
05/05/2005
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
Title:
|
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2009
|
Application #:
|
11125200
|
Filing Dt:
|
05/10/2005
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
Title:
|
TELEPHONE COMMUNICATION SYSTEM AND METHOD OVER LOCAL AREA NETWORK WIRING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
11125380
|
Filing Dt:
|
05/09/2005
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE FOR SIMULTANEOUSLY TESTING BLOCKS OF CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
11128229
|
Filing Dt:
|
05/13/2005
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
Title:
|
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11128383
|
Filing Dt:
|
05/13/2005
|
Publication #:
|
|
Pub Dt:
|
11/24/2005
| | | | |
Title:
|
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
11141568
|
Filing Dt:
|
05/31/2005
|
Publication #:
|
|
Pub Dt:
|
12/01/2005
| | | | |
Title:
|
DIFFERENTIAL TYPE DELAY CELLS AND METHODS OF OPERATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
11147629
|
Filing Dt:
|
06/08/2005
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
DUTY CYCLE CORRECTION CIRCUIT FOR USE IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
11156140
|
Filing Dt:
|
06/17/2005
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
Title:
|
FREQUENCY DIVISION MULTIPLEXING SYSTEM WITH SELECTABLE RATE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
11166620
|
Filing Dt:
|
06/24/2005
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
CIRCUIT AND METHOD FOR GENERATING WORDLINE VOLTAGE IN NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11187994
|
Filing Dt:
|
07/25/2005
|
Publication #:
|
|
Pub Dt:
|
11/17/2005
| | | | |
Title:
|
TELEPHONE COMMUNICATION SYSTEM AND METHOD OVER LOCAL AREA NETWORK WIRING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
11190884
|
Filing Dt:
|
07/28/2005
|
Publication #:
|
|
Pub Dt:
|
11/24/2005
| | | | |
Title:
|
LOCAL AREA NETWORK FOR DISTRIBUTING DATA COMMUNICATION, SENSING AND CONTROL SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
11195257
|
Filing Dt:
|
08/01/2005
|
Publication #:
|
|
Pub Dt:
|
12/01/2005
| | | | |
Title:
|
DELAY LOCKED LOOP IMPLEMENTATION IN A SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
11195641
|
Filing Dt:
|
08/03/2005
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
Title:
|
VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
11203046
|
Filing Dt:
|
08/12/2005
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11204660
|
Filing Dt:
|
08/15/2005
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
METHOD FOR FORMING STORAGE NODE OF CAPACITOR IN SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
11205082
|
Filing Dt:
|
08/17/2005
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
Title:
|
TIMING VERNIER USING A DELAY LOCKED LOOP
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
11206529
|
Filing Dt:
|
08/18/2005
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
Title:
|
CONTIGUOUS BLOCK ADDRESSING SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
11207017
|
Filing Dt:
|
08/18/2005
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
Title:
|
CONTIGUOUS BLOCK ADDRESSING SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
11207105
|
Filing Dt:
|
08/18/2005
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
Title:
|
CONTIGUOUS BLOCK ADDRESSING SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
11234302
|
Filing Dt:
|
09/26/2005
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
11234314
|
Filing Dt:
|
09/26/2005
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
11238973
|
Filing Dt:
|
09/30/2005
|
Publication #:
|
|
Pub Dt:
|
04/05/2007
| | | | |
Title:
|
POWER UP CIRCUIT WITH LOW POWER SLEEP MODE OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11238975
|
Filing Dt:
|
09/30/2005
|
Publication #:
|
|
Pub Dt:
|
04/05/2007
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING CURRENT LEAKAGE REDUCTION SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2009
|
Application #:
|
11257525
|
Filing Dt:
|
10/25/2005
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR PACKET ENCRYPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11261493
|
Filing Dt:
|
10/31/2005
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
11263144
|
Filing Dt:
|
10/31/2005
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
SORTING METHOD AND APPARATUS USING A CAM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
11264011
|
Filing Dt:
|
11/02/2005
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11264283
|
Filing Dt:
|
10/31/2005
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
PHASE-LOCKED LOOP CIRCUITRY USING CHARGE PUMPS WITH CURRENT MIRROR CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
11268760
|
Filing Dt:
|
11/08/2005
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
SYNCHRONOUS DRAM WITH SELECTABLE INTERNAL PREFETCH SIZE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
11269659
|
Filing Dt:
|
11/09/2005
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
MATCHLINE SENSE CIRCUIT AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
11272775
|
Filing Dt:
|
11/15/2005
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
11274276
|
Filing Dt:
|
11/16/2005
|
Publication #:
|
|
Pub Dt:
|
04/13/2006
| | | | |
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11287335
|
Filing Dt:
|
11/28/2005
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR PROVIDING DC POWER ON LOCAL TELEPHONE LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11289428
|
Filing Dt:
|
11/30/2005
|
Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT HAVING LOW POWER CONSUMPTION WITH SELF-REFRESH
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
11293124
|
Filing Dt:
|
12/05/2005
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
METHOD OF INHIBITING DEGRADATION OF GATE OXIDE FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11295492
|
Filing Dt:
|
12/07/2005
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11298978
|
Filing Dt:
|
12/09/2005
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
CHEMICAL VAPOR DEPOSITION OF TITANIUM FROM TITANIUM TETRACHLORIDE AND HYDROCARBON REACTANTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
11300313
|
Filing Dt:
|
12/15/2005
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
11305433
|
Filing Dt:
|
12/14/2005
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES
|
|