Total properties:
14
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2004
|
Application #:
|
10150685
|
Filing Dt:
|
05/17/2002
|
Publication #:
|
|
Pub Dt:
|
11/20/2003
| | | | |
Title:
|
DISTRIBUTED RAM IN A LOGIC ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
10164455
|
Filing Dt:
|
06/06/2002
|
Publication #:
|
|
Pub Dt:
|
12/12/2002
| | | | |
Title:
|
CELL ARCHITECTURE TO REDUCE CUSTOMIZATION IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2005
|
Application #:
|
10234926
|
Filing Dt:
|
09/04/2002
|
Publication #:
|
|
Pub Dt:
|
12/25/2003
| | | | |
Title:
|
LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
10904411
|
Filing Dt:
|
11/09/2004
|
Title:
|
CUSTOMIZATION OF STRUCTURED ASIC DEVICES USING PRE-PROCESS EXTRACTION OF ROUTING INFORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
10906527
|
Filing Dt:
|
02/23/2005
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
Title:
|
CONFIGURABLE INTEGRATED CIRCUIT CAPACITOR ARRAY USING VIA MASK LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
10907456
|
Filing Dt:
|
04/01/2005
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
Title:
|
VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
11023860
|
Filing Dt:
|
12/28/2004
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11469189
|
Filing Dt:
|
08/31/2006
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
CREATING HIGH-DRIVE LOGIC DEVICES FROM STANDARD GATES WITH MINIMAL USE OF CUSTOM MASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11782616
|
Filing Dt:
|
07/24/2007
|
Publication #:
|
|
Pub Dt:
|
11/15/2007
| | | | |
Title:
|
LOGIC ARRAY DEVICES HAVING COMPLEX MACRO-CELL ARCHITECTURE AND METHODS FACILITATING USE OF SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
11850791
|
Filing Dt:
|
09/06/2007
|
Publication #:
|
|
Pub Dt:
|
03/12/2009
| | | | |
Title:
|
CONFIGURING STRUCTURED ASIC FABRIC USING TWO NON-ADJACENT VIA LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
11965069
|
Filing Dt:
|
12/27/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
CONFIGURABLE INTEGRATED CIRCUIT CAPACITOR ARRAY USING VIA MASK LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
12246802
|
Filing Dt:
|
10/07/2008
|
Publication #:
|
|
Pub Dt:
|
02/05/2009
| | | | |
Title:
|
VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12268919
|
Filing Dt:
|
11/11/2008
|
Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
VIA CONFIGURABLE ARCHITECTURE FOR CUSTOMIZATION OF ANALOG CIRCUITRY IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12432494
|
Filing Dt:
|
04/29/2009
|
Publication #:
|
|
Pub Dt:
|
08/20/2009
| | | | |
Title:
|
USING SELECTABLE IN-LINE INVERTERS TO REDUCE THE NUMBER OF INVERTERS IN A SEMICONDUCTOR DESIGN
|
|