Total properties:
19
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
09594765
|
Filing Dt:
|
06/16/2000
|
Title:
|
TELEPHONE COMMUNICATION SYSTEM OVER A SINGLE TELEPHONE LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
10694761
|
Filing Dt:
|
10/29/2003
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
Title:
|
ERROR CORRECTION SCHEME FOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11637175
|
Filing Dt:
|
12/12/2006
|
Publication #:
|
|
Pub Dt:
|
06/12/2008
| | | | |
Title:
|
MEMORY SYSTEM AND METHOD WITH SERIAL AND PARALLEL MODES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
|
Application #:
|
11780231
|
Filing Dt:
|
07/19/2007
|
Publication #:
|
|
Pub Dt:
|
01/22/2009
| | | | |
Title:
|
MEMORY SYSTEM HAVING INCORRUPTED STROBE SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2009
|
Application #:
|
11830077
|
Filing Dt:
|
07/30/2007
|
Publication #:
|
|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
ERROR CORRECTION SCHEME FOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12337038
|
Filing Dt:
|
12/17/2008
|
Publication #:
|
|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
12412968
|
Filing Dt:
|
03/27/2009
|
Publication #:
|
|
Pub Dt:
|
07/23/2009
| | | | |
Title:
|
MEMORY SYSTEM AND METHOD WITH SERIAL AND PARALLEL MODES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12499577
|
Filing Dt:
|
07/08/2009
|
Publication #:
|
|
Pub Dt:
|
11/05/2009
| | | | |
Title:
|
MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
13114523
|
Filing Dt:
|
05/24/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
13154891
|
Filing Dt:
|
06/07/2011
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13481888
|
Filing Dt:
|
05/28/2012
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
14044449
|
Filing Dt:
|
10/02/2013
|
Publication #:
|
|
Pub Dt:
|
04/02/2015
| | | | |
Title:
|
VERTICAL GATE STACKED NAND AND ROW DECODER FOR ERASE OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2015
|
Application #:
|
14046281
|
Filing Dt:
|
10/04/2013
|
Publication #:
|
|
Pub Dt:
|
10/16/2014
| | | | |
Title:
|
U-SHAPED COMMON-BODY TYPE CELL STRING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
14460963
|
Filing Dt:
|
08/15/2014
|
Publication #:
|
|
Pub Dt:
|
04/09/2015
| | | | |
Title:
|
Cell Array with a Manufacturable Select Gate for a Nonvolatile Semiconductor Memory Device
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
14496797
|
Filing Dt:
|
09/25/2014
|
Publication #:
|
|
Pub Dt:
|
04/16/2015
| | | | |
Title:
|
COST EFFECTIVE METHOD OF FORMING EMBEDDED DRAM CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
|
Application #:
|
14532048
|
Filing Dt:
|
11/04/2014
|
Publication #:
|
|
Pub Dt:
|
05/14/2015
| | | | |
Title:
|
Three Dimensional Nonvolatile Memory Cell Structure with Upper Body Connection
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2017
|
Application #:
|
14926484
|
Filing Dt:
|
10/29/2015
|
Publication #:
|
|
Pub Dt:
|
02/18/2016
| | | | |
Title:
|
VERTICAL GATE STACKED NAND AND ROW DECODER FOR ERASE OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2017
|
Application #:
|
14938259
|
Filing Dt:
|
11/11/2015
|
Publication #:
|
|
Pub Dt:
|
03/03/2016
| | | | |
Title:
|
U-SHAPED COMMON-BODY TYPE CELL STRING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2018
|
Application #:
|
15422853
|
Filing Dt:
|
02/02/2017
|
Publication #:
|
|
Pub Dt:
|
05/25/2017
| | | | |
Title:
|
U-SHAPED COMMON-BODY TYPE CELL STRING
|
|