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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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08950444
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Filing Dt:
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10/15/1997
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Title:
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FIELD PROGRAMMABLE GATE ARRAY HAVING A DEDICATED PROCESSOR INTERFACE
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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08950446
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Filing Dt:
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10/15/1997
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Title:
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BI-DIRECTIONAL BUFFERS AND SUPPLEMENTAL LOGIC AND INTERCONNECT CELLS FOR PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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08950448
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Filing Dt:
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10/15/1997
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Title:
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PROGRAMMABLE CLOCK MANAGER FOR A PROGRAMMABLE LOGIC DEVICE THAT CAN BE PROGRAMMED WITHOUT RECONFIGURING THE DEVICE
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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08950624
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Filing Dt:
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10/15/1997
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH LOGIC CELLS HAVING A FLEXIBLE INPUT STRUCTURE
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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08951128
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Filing Dt:
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10/15/1997
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Title:
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PROGRAMMABLE CLOCK MANAGER FOR A PROGRAMMABLE LOGIC DEVICE THAT CAN IMPLEMENT DELAY-LOCKED LOOP FUNCTIONS
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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08964421
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Filing Dt:
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11/04/1997
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Publication #:
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Pub Dt:
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11/15/2001
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Title:
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SIMULTANEOUS WIRED AND WIRELESS REMOTE IN-SYSTEM PROGRAMMING OF MULTIPLE REMOTE SYSTEMS
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08974799
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Filing Dt:
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11/20/1997
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Title:
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METHOD FOR TESTING FIELD PROGRAMMABLE GATE ARRAYS
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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08995612
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Filing Dt:
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12/22/1997
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Title:
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FLEXIBLE DIRECT CONNECTIONS BETWEEN INPUT/OUTPUT BLOCKS (IOBS) AND VARIABLE GRAIN BLOCKS (VGBS) IN FPGA INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08995614
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Filing Dt:
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12/22/1997
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Title:
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INPUT/OUTPUT BLOCK (IOB) CONNECTIONS TO MAXL LINES NOR LINES AND DENDRITES IN FPGA INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08995615
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Filing Dt:
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12/22/1997
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Title:
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PROGRAMMABLE INPUT/OUTPUT BLOCK (IOB) IN FPGA INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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08996049
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Filing Dt:
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12/22/1997
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Title:
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DUAL PORT SRAM MEMORY FOR RUN TIME USE IN FPGA INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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08996119
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Filing Dt:
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12/22/1997
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Title:
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MULTIPLE INPUT ZERO POWER AND /NOR GATE FOR USE IN A FIELD PROGRAMMABLE GATE ARRAY (FPGA)
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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08996361
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Filing Dt:
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12/22/1997
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Title:
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SYMMETICAL, EXTENDED AND FAST DIRECT CONNECTIONS BETWEEN VARIABLE GRAIN BLOCKS IN FPGA INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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08996530
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Filing Dt:
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12/23/1997
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Title:
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PROCESS FOR PROGRAMMING PLDS AND EMBEDDED NON-VOLATILE MEMORIES
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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08997221
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Filing Dt:
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12/22/1997
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Title:
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PROGRAMMABLE CONTROL MULTIPLEXING FOR INPUT/OUTPUT BLOCKS (IOBS) IN FPGA INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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08998978
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Filing Dt:
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12/29/1997
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Title:
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ELECTRICALLY ERASABLE AND REPROGRAMMABLE, NONVOLATILE INTEGRATED STORAGE DEVICE WITH IN-SYSTEM PROGRAMMING AND VERIFICATION (ISPAV) CAPABILITIES FOR SUPPORTING IN-SYSTEM RECONFIGURING OF PLD'S
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Patent #:
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Issue Dt:
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10/10/2000
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Application #:
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09008762
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Filing Dt:
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01/19/1998
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Title:
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SYNTHESIS-FRIENDLY FPGA ARCHITECTURE WITH VARIABLE LENGTH AND VARIABLE TIMING INTERCONNECT
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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09010000
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Filing Dt:
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01/21/1998
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Title:
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VIRTUAL LOGIC SYSTEM FOR RECONFIGURABLE HARDWARE
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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09023506
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Filing Dt:
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02/13/1998
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Title:
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SEQUENTIAL AND SIMULTANEOUS MANUFACTURING PROGRAMMING OF MULTIPLE IN-SYSTEM PROGRAMMABLE SYSTEMS THROUGH A DATA NETWORK
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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09023669
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Filing Dt:
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02/10/1998
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Title:
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SPACER-BASED ANTIFUSE STRUCTURE FOR LOW CAPACITANCE AND HIGH RELIABILITY AND METHOD OF FABRICATION THEREOF
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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09026814
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Filing Dt:
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02/20/1998
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Title:
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EEPROM CELL WITH FIELD-EDGELESS TUNNEL WINDOW USING SHALLOW TRENCH ISOLATION PROCESS
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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09037095
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Filing Dt:
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03/09/1998
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Title:
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PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE, INPUT/OUTPUT STRUCTURE AND CONFIGUABLE LOGIC BLOCK
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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09045128
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Filing Dt:
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03/20/1998
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Title:
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GLOBAL SIGNAL DISTRIBUTION WITH REDUCED ROUTING TRACKS IN AN FPGA
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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09046404
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Filing Dt:
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03/23/1998
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Title:
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AN ENHANCED METHOD OF TESTING SEMICONDUCTOR DEVICES HAVING NONVOLATILE ELEMENTS
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09053251
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Filing Dt:
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03/31/1998
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Title:
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OFFSET VOLTAGE CALIBRATION DAC WITH REDUCED SENSITIVITY TO MISMATCH ERRORS
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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09059552
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Filing Dt:
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04/13/1998
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Title:
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METHOD OF TESTING AND DIAGNOSING FIELD PROGRAMMABLE GATE ARRAYS
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09067318
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Filing Dt:
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04/27/1998
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Title:
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PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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09067320
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Filing Dt:
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04/27/1998
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Title:
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INTERNAL TRISTATE BUS WITH ARBITRATION LOGIC
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09069035
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Filing Dt:
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04/27/1998
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Title:
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COMBINATION OF GLOBAL CLOCK AND LOCALIZED CLOCKS
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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09069768
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Filing Dt:
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04/30/1998
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Title:
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NON-VOLATILE MEMORY ELEMENT FOR PROGRAMMABLE LOGIC APPLICATIONS AND OPERATIONAL METHODS THEREFOR
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Patent #:
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Issue Dt:
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05/01/2001
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Application #:
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09080906
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Filing Dt:
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05/18/1998
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Title:
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PACKAGE MIGRATION FOR RELATED PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09083205
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Filing Dt:
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05/21/1998
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Title:
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PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09083335
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Filing Dt:
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05/21/1998
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Title:
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METHOD AND STRUCTURE FOR DYNAMIC IN-SYSTEM PROGRAMMING
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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09083336
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Filing Dt:
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05/21/1998
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Title:
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PROGRAMMABLE OUTPUT VOLTAGE LEVELS
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09086437
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Filing Dt:
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05/28/1998
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Title:
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STACKED TUNNELING DIELECTRIC TECHNOLOGY FOR IMPROVING DATA RETENTION OF EEPROM CELL
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09109123
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Filing Dt:
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06/30/1998
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Title:
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METHOD AND APPARATUS FOR TESTING FIELD PROGRAMMABLE GATE ARRAYS
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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09114385
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Filing Dt:
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07/13/1998
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Title:
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ELECTROSTATIC DISCHARGE (ESD) PROTECTION FOR A 5.0 VOLT COMPATIBLE INPUT/OUTPUT (I/O) IN A 2.5 VOLT SEMICONDUCTOR PROCESS
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09114717
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Filing Dt:
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07/13/1998
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Title:
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ELECTROSTATIC DISCHARGE (ESD) PROTECTION FOR NMOS PULL UP TRANSISTORS OF A 5.0 VOLT COMPATIBLE OUTPUT BUFFER USING 2.5 VOLT PROCESS TRANSISTORS
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09114718
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Filing Dt:
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07/13/1998
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Title:
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BALLAST RESISTORS WITH PARALLEL STACKED NMOS TRANSISTORS USED TO PREVENT SECONDARY BREAKDOWN DURING ESD WITH 2.5 VOLT PROCESS TRANSISTORS
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Patent #:
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|
Issue Dt:
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09/26/2000
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Application #:
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09115683
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Filing Dt:
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07/15/1998
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Title:
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SIGNALING VOLTAGE RANGE DISCRIMINATOR
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Patent #:
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|
Issue Dt:
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02/22/2000
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Application #:
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09118200
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Filing Dt:
|
07/17/1998
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Title:
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FLEXIBLE SYNCHRONOUS/AND ASYNCHRONOUS CIRCUITS FOR A VERY HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
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Patent #:
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|
Issue Dt:
|
05/16/2000
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Application #:
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09134174
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Filing Dt:
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08/14/1998
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Title:
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DATA RETENTION OF EEPROM CELL WITH SHALLOW TRENCH ISOLATION USING THICKER LINER OXIDE
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Patent #:
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|
Issue Dt:
|
07/11/2000
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Application #:
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09145793
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Filing Dt:
|
09/02/1998
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Title:
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HIGH SPEED LINE DRIVER WITH DIRECT AND COMPLEMENTARY OUTPUTS
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Patent #:
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|
Issue Dt:
|
07/23/2002
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Application #:
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09169492
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Filing Dt:
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10/09/1998
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Publication #:
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|
Pub Dt:
|
11/22/2001
| | | | |
Title:
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EEPROM CELL WITH SELF-ALIGNED TUNNELING WINDOW
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Patent #:
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|
Issue Dt:
|
02/12/2002
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Application #:
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09169848
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Filing Dt:
|
10/09/1998
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Title:
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TEST CIRCUITS FOR TESTING INTER-DEVICE FPGA LINKS INCLUDING A SHIFT REGISTER CONFIGURED FROM FPGA ELEMENTS TO FORM A SHIFT BLOCK THROUGH SAID INTER-DEVICE FPGA LINKS
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Patent #:
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|
Issue Dt:
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05/08/2001
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Application #:
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09186917
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Filing Dt:
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11/06/1998
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Title:
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PROGRAMMABLE INTEGRATED CIRCUIT DEVICE WITH SLEW CONTROL AND SKEW CONTROL
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Patent #:
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|
Issue Dt:
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11/28/2000
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Application #:
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09187689
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Filing Dt:
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11/05/1998
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Title:
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TILEABLE AND COMPACT LAYOUT FOR SUPER VARIABLE GRAIN BLOCKS WITHIN FPGA DEVICE
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Patent #:
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|
Issue Dt:
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05/08/2001
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Application #:
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09187691
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Filing Dt:
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11/05/1998
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Title:
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SEMICONDUCTOR-OXIDE-SEMICONDUCTOR CAPACITOR FORMED IN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
01/02/2001
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Application #:
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09188778
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Filing Dt:
|
11/09/1998
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Title:
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HIGH VOLTAGE SWITCH FOR PROVIDING VOLTAGES HIGHER THAN 2.5 VOLTS WITH TRANSISTORS MADE USING A 2.5 VOLT PROCESS
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Patent #:
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|
Issue Dt:
|
09/18/2001
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Application #:
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09192094
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Filing Dt:
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11/13/1998
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Title:
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OPTIMIZATION OF S/D ANNEALING TO MINIMIZE S/D SHORTS IN MEMORY ARRAY
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Patent #:
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|
Issue Dt:
|
04/24/2001
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Application #:
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09192096
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Filing Dt:
|
11/13/1998
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Title:
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REDUCTION OF MECHANICAL STRESS IN SHALLOW TRENCH ISOLATION PROCESS
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Patent #:
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|
Issue Dt:
|
06/15/1999
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Application #:
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09196080
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Filing Dt:
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11/19/1998
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Title:
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POWER CONVERTER WITH 2.5 VOLT SEMICONDUCTOR PROCESS COMPONENTS
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09196449
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Filing Dt:
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11/19/1998
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Title:
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ENHANCED I/O CONTROL FLEXIBILITY FOR GENERATING CONTROL SIGNALS
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Patent #:
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Issue Dt:
|
12/28/1999
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Application #:
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09198653
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Filing Dt:
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11/24/1998
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Title:
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EEPROM DEVICE HAVING IMPROVED DATA RETENTION AND OPERATING METHOD
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Patent #:
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|
Issue Dt:
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04/17/2001
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Application #:
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09198796
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Filing Dt:
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11/24/1998
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Title:
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VARIABLE SIZED LINE DRIVING AMPLIFIERS FOR INPUT/OUTPUT BLOCKS (IOBS) IN FPGA INTEGRATED CIRCUITS
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Patent #:
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|
Issue Dt:
|
03/05/2002
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Application #:
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09199664
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Filing Dt:
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11/25/1998
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Title:
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CLOCK TREE TOPOLOGY
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Patent #:
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|
Issue Dt:
|
07/17/2001
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Application #:
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09200395
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Filing Dt:
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11/24/1998
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Title:
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METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING HIGH RELIABILITY PASSIVATION OVERLYING A MULTI-LEVEL INTERCONNECT
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Patent #:
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Issue Dt:
|
10/17/2000
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Application #:
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09201081
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Filing Dt:
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11/30/1998
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Title:
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PHASE LOCKED LOOP WITH A LOCK DETECTOR
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Patent #:
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|
Issue Dt:
|
06/11/2002
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Application #:
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09203149
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Filing Dt:
|
12/01/1998
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Publication #:
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|
Pub Dt:
|
10/18/2001
| | | | |
Title:
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EEPROM CELL WITH TUNNELING ACROSS ENTIRE SEPARATED CHANNELS
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Patent #:
|
|
Issue Dt:
|
01/16/2001
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Application #:
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09207558
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Filing Dt:
|
12/08/1998
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Title:
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OPERATIONAL AMPLIFIER WITH CMOS TRANSISTORS MADE USING 2.5 VOLT PROCESS TRANSISTORS
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Patent #:
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|
Issue Dt:
|
12/19/2000
|
Application #:
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09208203
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Filing Dt:
|
12/09/1998
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Title:
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EFFICIENT INTERCONNECT NETWORK FOR USE IN FPGA DEVICE HAVING VARIABLE GRAIN ARCHITECTURE
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|
Patent #:
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|
Issue Dt:
|
09/26/2000
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Application #:
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09212022
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Filing Dt:
|
12/15/1998
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Title:
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METHODS FOR CONFIGURING FPGA'S HAVING VARIABLE GRAIN COMPONENTS FOR PROVIDING TIME-SHARED ACCESS TO INTERCONNECT RESOURCES
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Patent #:
|
|
Issue Dt:
|
08/08/2000
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Application #:
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09212330
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Filing Dt:
|
12/15/1998
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Title:
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METHODS FOR CONFIGURING FPGA'S HAVING VARIABLE GRAIN BLOCKS AND LOGIC FOR PROVIDING TIME-SHARED ACCESS TO INTERCONNECT RESOURCES
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|
Patent #:
|
|
Issue Dt:
|
06/27/2000
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Application #:
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09212331
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Filing Dt:
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12/15/1998
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Title:
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FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS EACH WITH STATICALLY AND DYNAMICALLY CONTROLLABLE READ MODE
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09216051
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Filing Dt:
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12/18/1998
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Title:
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METHOD OF FORMING A NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
|
03/20/2001
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Application #:
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09216662
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Filing Dt:
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12/16/1998
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Title:
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METHODS FOR CONFIGURING FPGA'S HAVING VARIABLE GRAIN BLOCKS AND SHARED LOGIC FOR PROVIDING SYMMETRIC ROUTING OF RESULT OUTPUT TO DIFFERENTLY-DIRECTED AND TRISTATEABLE INTERCONNECT RESOURCES
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09217646
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Filing Dt:
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12/21/1998
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Title:
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METHOD OF FABRICATING PROGRAMMING AND ERASING A DUAL POCKET TWO
SIDED PROGRAM/ERASE NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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09217647
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Filing Dt:
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12/21/1998
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Title:
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EEPROM CELL USING P-WELL FOR TUNNELING ACROSS A CHANNEL
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09217648
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Filing Dt:
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12/21/1998
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Title:
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FLOATING GATE MEMORY CELL STRUCTURE WITH PROGRAMMING MECHANISM OUTSIDE THE READ PATH
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09218987
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Filing Dt:
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12/22/1998
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Title:
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EEPROM CELL WITH TUNNELING AT SEPARATE EDGE AND CHANNEL REGIONS
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09220469
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Filing Dt:
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12/23/1998
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Title:
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AVALANCHE PROGRAMMED FLOATING GATE MEMORY CELL STRUCTURE WITH PROGRAM ELEMENT IN FIRST POLYSILICON LAYER
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09221360
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Filing Dt:
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12/28/1998
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Title:
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AVALANCHE PROGRAMMED FLOATING GATE MEMORY CELL STRUCTURE WITH PROGRAM ELEMENT IN POLYSILICON
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09226702
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Filing Dt:
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01/07/1999
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Title:
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PMOS AVALANCHE PROGRAMMED FLOATING GATE MEMORY CELL STRUCTURE
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09227981
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Filing Dt:
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01/08/1999
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Title:
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OXIDE FORMATION PROCESS FOR MANUFACTURING PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09235351
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Filing Dt:
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01/21/1999
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Title:
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FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS AND INTERCONNECT CHANNEL FOR BROADCASTING ADDRESS AND CONTROL SIGNALS
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09235356
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Filing Dt:
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01/21/1999
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Title:
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MULTI-PORT SRAM CELL ARRAY HAVING PLURAL WRITE PATHS INCLUDING FOR WRITING THROUGH ADDRESSABLE PORT AND THROUGH SERIAL BOUNDARY SCAN
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09235615
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Filing Dt:
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01/21/1999
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Title:
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FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS WITH REGISTERED ADDRESS AND DATA INPUT SECTIONS
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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09239072
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Filing Dt:
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01/27/1999
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Title:
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TWO TRANSISTOR EEPROM CELL USING P-WELL FOR TUNNELING ACROSS A CHANNEL
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09240560
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Filing Dt:
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01/29/1999
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Title:
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PROCESS FOR MANUFACTURING SHALLOW TRENCHES FILLED WITH DIELECTRIC MATERIAL HAVING LOW MECHANICAL STRESS
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09245813
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Filing Dt:
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02/05/1999
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Title:
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TWO TRANSISTOR EEPROM CELL
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09255053
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Filing Dt:
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02/22/1999
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Title:
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PROCESS FOR FABRICATING A HIGH-ENDURANCE NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09255410
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Filing Dt:
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02/22/1999
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Title:
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METHOD FOR SORTING SEMICONDUCTOR DEVICES HAVING A PLURALITY OF NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09256245
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Filing Dt:
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02/23/1999
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Title:
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FABRICATION OF OXIDE REGIONS HAVING MULTIPLE THICKNESSES USING MINIMIZED NUMBER OF THERMAL CYCLES
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09261776
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Filing Dt:
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03/03/1999
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Title:
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FAULT TOLERANT OPERATION OF FIELD PROGRAMMABLE GATE ARRAYS
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09263412
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Filing Dt:
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03/05/1999
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Title:
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SEMICONDUCTOR DEVICE HAVING A MULTI-LAYER METAL INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09268897
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Filing Dt:
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03/16/1999
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Title:
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NON-VOLATILE MEMORY DEVICE HAVING A HIGH-RELIABILITY COMPOSITE INSULATON LAYER
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09276990
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Filing Dt:
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03/26/1999
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Title:
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HIGH VOLTAGE DETECTOR TO CONTROL A POWER SUPPLY VOLTAGE PUMP FOR A 2.5 VOLT SEMICONDUCTOR PROCESS DEVICE
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Patent #:
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Issue Dt:
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02/29/2000
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Application #:
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09276991
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Filing Dt:
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03/26/1999
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Title:
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BAND GAP REFERENCE USING A LOW VOLTAGE POWER SUPPLY
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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09277441
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Filing Dt:
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03/26/1999
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Title:
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AVALANCHE INJECTION EEPROM MEMORY CELL WITH P-TYPE CONTROL GATE
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09280887
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Filing Dt:
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03/29/1999
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Title:
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BORON DOPED SILICON CAPACITOR PLATE
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09286830
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Filing Dt:
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04/06/1999
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Title:
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ANGLED NITROGEN ION IMPLANTATION FOR MINIMIZING MECHANICAL STRESS ON SIDE WALLS OF AN ISOLATION TRENCH
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09287976
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Filing Dt:
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04/07/1999
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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HIGH DIELECTRIC GATE INSULATOR PROCESS FOR NANOMETER MOSFETS
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09288062
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Filing Dt:
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04/07/1999
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Title:
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HIGH SPEED LOGICAL OR CIRCUIT
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Patent #:
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|
Issue Dt:
|
07/23/2002
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Application #:
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09310071
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Filing Dt:
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05/11/1999
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Title:
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FLOATING GATE MEMORY APPARATUS AND METHOD FOR SELECTED PROGRAMMING THEREOF
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Patent #:
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|
Issue Dt:
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08/14/2001
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Application #:
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09316241
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Filing Dt:
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05/21/1999
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Title:
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TRIPLE-WELL EEPROM CELL USING P-WELL FOR TUNNELING ACROSS A CHANNEL
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Patent #:
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|
Issue Dt:
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04/22/2003
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Application #:
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09318570
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Filing Dt:
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05/26/1999
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Title:
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CURRENT-CONTROLLED HIGH VOLTAGE DISCHARGE SCHEME
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Patent #:
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|
Issue Dt:
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09/12/2000
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Application #:
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09320389
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Filing Dt:
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05/26/1999
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Title:
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ELECTRICALLY ERASABLE NON-VOLATILE MEMORY CELL WITH INTEGRATED SCRAM CELL TO REDUCE TESTING TIME
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|
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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09320392
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Filing Dt:
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05/26/1999
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Title:
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ELECTRICALLY ERASABLE NON-VOLATILE MEMORY CELL WITH NO POWER DISSIPATION
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|
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09326140
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Filing Dt:
|
06/06/1999
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Title:
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ENHANCED MACROCELL MODULE FOR HIGH DENSITY CPLD ARCHITECTURES
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|
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Patent #:
|
|
Issue Dt:
|
02/06/2001
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Application #:
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09326940
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Filing Dt:
|
06/06/1999
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Title:
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SCALABLE ARCHITECTURE FOR HIGH DENSITY CPLD'S HAVING TWO-LEVEL HIERARACHY OF ROUTING RESOURCES
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