|
Total properties:
25
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
08857269
|
Filing Dt:
|
05/16/1997
|
|
Title:
|
LEVEL CONVERTER AND SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09000739
|
Filing Dt:
|
12/30/1997
|
|
Title:
|
A LOW DIELECTRIC CONSTANT MATERIAL AND METHOD OF APPLICATION TO ISOLATE CONDUCTIVE LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09040107
|
Filing Dt:
|
03/17/1998
|
|
Title:
|
NEW APPROACH FOR THE FORMATION OF SEMICONDUCTOR DEVICES WHICH REDUCES BAND-TO-BAND TUNNELING CURRENT AND SHORT-CHANNEL EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09076662
|
Filing Dt:
|
05/12/1998
|
|
Title:
|
METHODS FOR REMOVING SILICIDE RESIDUE IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09085680
|
Filing Dt:
|
05/27/1998
|
|
Title:
|
METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY(EEPROM)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09109664
|
Filing Dt:
|
07/02/1998
|
|
Title:
|
LOW VOLTAGE JUNCTION AND HIGH VOLTAGE JUNCTION OPTIMIZATION FOR FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09118375
|
Filing Dt:
|
07/17/1998
|
|
Title:
|
METHOD FOR ETCHING LAYERS ON A SEMICONDUCTOR WAFER IN A SINGLE ETCHING CHAMBER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09119777
|
Filing Dt:
|
07/21/1998
|
|
Title:
|
LOW TEMPERATURE PHOTORESIST REMOVAL FOR REWORK DURING METAL MASK FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09170061
|
Filing Dt:
|
10/13/1998
|
|
Title:
|
METHOD OF FORMING A COMPOSITE INTERPOLY GATE DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09177817
|
Filing Dt:
|
10/23/1998
|
|
Title:
|
HIGH VOLTAGE TRANSISTOR WITH HIGH GATED DIODE BREAKDOWN VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09266714
|
Filing Dt:
|
03/11/1999
|
|
Title:
|
AMMONIA ANNEALED AND WET OXIDIZED LPCVD OXIDE TO REPLACE ONO FILMS FOR HIGH INTEGRATED FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09336057
|
Filing Dt:
|
06/18/1999
|
|
Title:
|
METHOD OF SPACER FORMATION AND SOURCE PROTECTION AFTER SELF-ALIGNED SOURCE FORMED AND A DEVICE PROVIDED BY SUCH A METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09370010
|
Filing Dt:
|
08/06/1999
|
|
Title:
|
MULTI STATE SENSING OF NAND MEMORY CELLS BY APPLYING REVERSE-BIAS VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09370380
|
Filing Dt:
|
08/09/1999
|
|
Title:
|
RAMPED GATE TECHNIQUE FOR SOFT PROGRAMMING TO TIGHTEN THE VT DISTRIBUTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09374059
|
Filing Dt:
|
08/12/1999
|
|
Title:
|
FLOATING GATE ENGINEERING TO IMPROVE TUNNEL OXIDE RELIABILITY FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09404078
|
Filing Dt:
|
09/23/1999
|
|
Title:
|
CONCURRENT ERASE VERIFY SCHEME FOR FLASH MEMORY APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09412278
|
Filing Dt:
|
10/05/1999
|
|
Title:
|
POST BARRIER METAL CONTACT IMPLANTATION TO MINIMIZE OUT DIFFUSION FOR NAND DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09421762
|
Filing Dt:
|
10/19/1999
|
|
Title:
|
SEPARATE OUTPUT POWER SUPPLY TO REDUCE OUTPUT NOISE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09421774
|
Filing Dt:
|
10/19/1999
|
|
Title:
|
COMMON FLASH INTERFACE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09430765
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
METHOD FOR FORMING FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09431296
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
FLASH MEMORY WORDLINE TRACKING ACROSS WHOLE CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09487922
|
Filing Dt:
|
01/19/2000
|
|
Title:
|
Process for fabricating a semiconductor device having a graded junction
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09490351
|
Filing Dt:
|
01/24/2000
|
|
Title:
|
METHOD TO PROVIDE A REDUCED CONSTANT E-FIELD DURING ERASE OF EEPROMS FOR RELIABILITY IMPROVEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09490352
|
Filing Dt:
|
01/24/2000
|
|
Title:
|
Background correction for charge gain and loss
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09498205
|
Filing Dt:
|
02/04/2000
|
|
Title:
|
Noise reduction during simultaneous operation of a flash memory device
|
|
