Patent Assignment Details
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Reel/Frame: | 005920/0357 | |
| Pages: | 3 |
| | Recorded: | 11/19/1991 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST. |
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Total properties:
1
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Patent #:
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Issue Dt:
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09/22/1992
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Application #:
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07795338
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Filing Dt:
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11/19/1991
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Title:
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METHOD OF PREVENTING STORAGE NODE TO STORAGE NODE SHORTS IN FABRICATION OF MEMORY INTEGRATED CIRCUITRY HAVING STACKED CAPACITORS AND STACKED CAPACITOR MEMORY INTEGRATED CIRCUITS
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Assignee
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2805 E. COLUMBIA RD., |
BOISE, IDAHO 83706 |
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Correspondence name and address
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WELLS, ST. JOHN AND ROBERTS
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W. 601 MAIN AVENUE
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SUITE 815
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SPOKANE, WA 99201-0679
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