Patent Assignment Details
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| Reel/Frame: | 025438/0357 | |
| Pages: | 2 |
| | Recorded: | 12/02/2010 | | |
| Attorney Dkt #: | 03PA053US01D01 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09757067
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Filing Dt:
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01/08/2001
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Title:
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System, IC chip, on-chip test structure, and corresponding method for modeling one or more target interconnect capacitances
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Assignee
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| 2655 SEELY AVENUE |
| SAN JOSE, CALIFORNIA 95134 |
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Correspondence name and address
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LISSA OROS
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2655 SEELY AVENUE
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CADENCE DESIGN SYSTEMS, INC.
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SAN JOSE, CA 95134
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