Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 023075/0361 | |
| Pages: | 7 |
| | Recorded: | 08/11/2009 | | |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
9
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Patent #:
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Issue Dt:
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07/21/1998
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Application #:
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08554111
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Filing Dt:
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11/06/1995
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Title:
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ARRANGEMENT OF PADS AND THROUGH-HOLES FOR SEMICONDUCTOR PACKAGES
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08932711
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Filing Dt:
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09/17/1997
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Title:
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INTERPOSER FOR BALL GRID ARRAY (BGA) PACKAGE
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09006813
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Filing Dt:
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01/14/1998
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Title:
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INTEGRATED CIRCUIT PACKAGE HAVING SIGNAL TRACES INTERPOSED BETWEEN POWER AND GROUND CONDUCTORS IN ORDER TO FORM STRIPLINE TRANSMISSION LINES
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09735980
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Filing Dt:
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12/13/2000
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Title:
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METHOD FOR INCREASING TRACE ROWS OF A BALL GRID ARRAY
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09781866
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Filing Dt:
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02/12/2001
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Title:
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LAYOUT OF VDD AND VSS BALLS IN A FOUR LAYER PBGA
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09894718
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Filing Dt:
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06/27/2001
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Title:
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TAPE DESIGN TO REDUCE WARPAGE
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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10105863
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Filing Dt:
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03/25/2002
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Title:
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INTEGRATED CIRCUIT PACKAGE SUBSTRATE WITH HIGH DENSITY ROUTING MECHANISM
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Patent #:
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Issue Dt:
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11/30/2004
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Application #:
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10387261
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Filing Dt:
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03/11/2003
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Publication #:
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Pub Dt:
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12/18/2003
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Title:
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PBGA ELECTRICAL NOISE ISOLATION OF SIGNAL TRACES
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Patent #:
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Issue Dt:
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02/05/2008
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Application #:
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11205364
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Filing Dt:
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08/17/2005
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Publication #:
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Pub Dt:
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02/22/2007
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Title:
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TWO LAYER SUBSTRATE BALL GRID ARRAY DESIGN
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Assignee
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| 1621BARBER LANE |
| MS: D-105 LEGAL |
| MILPITAS, CALIFORNIA 95035 |
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Correspondence name and address
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LSI CORPORATION
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1621 BARBER LANE
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MS: D-105 LEGAL
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MILPITAS, CA 95035
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