Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 005650/0362 | |
| Pages: | 3 |
| | Recorded: | 04/01/1991 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST. |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1993
|
Application #:
|
07619279
|
Filing Dt:
|
11/28/1990
|
|
Title:
|
MICROPROCESSOR MEMORY BUS INTERFACE FOR INHIBITING RELATCHING OF ROW ADDRESS PORTIONS UPON SUBSEQUENT ACCESSES INCLUDING A SAME ROW ADDRESS PORTION
|
|
|
Assignee
|
|
|
|
|
| A CORP. OF CA |
| PALO ALTO, CALIFORNIA |
|
|
Correspondence name and address
|
| |
RECORDS MANAGER, LEGAL DEPT. 20BO
|
| |
HEWLETT-PACKARD COMPANY
|
| |
P. O. BOX 10301
|
| |
PALO ALTO, CA 94303-0890
|
Search Results as of:
06/25/2024 09:48 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
