Total properties:
1086
Page
7
of
11
Pages:
1 2 3 4 5 6 7 8 9 10 11
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13871411
|
Filing Dt:
|
04/26/2013
|
Title:
|
METHODS AND SYSTEMS FOR GATE DIMENSION CONTROL IN MULTI-GATE STRUCTURES FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2015
|
Application #:
|
13872643
|
Filing Dt:
|
04/29/2013
|
Publication #:
|
|
Pub Dt:
|
10/30/2014
| | | | |
Title:
|
SELECTIVE GATE OXIDE PROPERTIES ADJUSTMENT USING FLUORINE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13873454
|
Filing Dt:
|
04/30/2013
|
Publication #:
|
|
Pub Dt:
|
09/19/2013
| | | | |
Title:
|
AMPLIFIERS AND RELATED RECEIVER SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13873988
|
Filing Dt:
|
04/30/2013
|
Title:
|
SYNCHRONOUS MULTIPLE PORT MEMORY WITH ASYNCHRONOUS PORTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13873998
|
Filing Dt:
|
04/30/2013
|
Publication #:
|
|
Pub Dt:
|
10/30/2014
| | | | |
Title:
|
FOUR PORT MEMORY WITH MULTIPLE CORES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13874119
|
Filing Dt:
|
04/30/2013
|
Publication #:
|
|
Pub Dt:
|
10/30/2014
| | | | |
Title:
|
NON-VOLATILE MEMORY (NVM) WITH VARIABLE VERIFY OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
13874127
|
Filing Dt:
|
04/30/2013
|
Publication #:
|
|
Pub Dt:
|
10/30/2014
| | | | |
Title:
|
BIASING SPLIT GATE MEMORY CELL DURING POWER-OFF MODE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2015
|
Application #:
|
13875618
|
Filing Dt:
|
05/02/2013
|
Publication #:
|
|
Pub Dt:
|
11/06/2014
| | | | |
Title:
|
Electrostatic Discharge (ESD) Clamp Circuit with High Effective Holding Voltage
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
13880193
|
Filing Dt:
|
04/18/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICE AND METHOD FOR DETECTING AN EXCESSIVE VOLTAGE STATE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13887233
|
Filing Dt:
|
05/03/2013
|
Publication #:
|
|
Pub Dt:
|
11/06/2014
| | | | |
Title:
|
TESTING AN ELECTRICAL CONNECTION OF A DEVICE CAP
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
13890394
|
Filing Dt:
|
05/09/2013
|
Publication #:
|
|
Pub Dt:
|
11/13/2014
| | | | |
Title:
|
METAL-OXIDE-SEMICONDUCTOR (MOS) VOLTAGE DIVIDER WITH DYNAMIC IMPEDANCE CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
13892293
|
Filing Dt:
|
05/12/2013
|
Publication #:
|
|
Pub Dt:
|
11/13/2014
| | | | |
Title:
|
INTEGRATED CIRCUIT POWER MANAGEMENT MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13895344
|
Filing Dt:
|
05/15/2013
|
Title:
|
SYSTEM FOR GENERATING CLOCK SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2016
|
Application #:
|
13900226
|
Filing Dt:
|
05/22/2013
|
Publication #:
|
|
Pub Dt:
|
11/27/2014
| | | | |
Title:
|
PROTECTION DEVICE AND RELATED FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2015
|
Application #:
|
13900256
|
Filing Dt:
|
05/22/2013
|
Publication #:
|
|
Pub Dt:
|
11/27/2014
| | | | |
Title:
|
PROTECTION DEVICE AND RELATED FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2015
|
Application #:
|
13901189
|
Filing Dt:
|
05/23/2013
|
Publication #:
|
|
Pub Dt:
|
11/27/2014
| | | | |
Title:
|
ACTIVE LATERAL FORCE STICTION SELF-RECOVERY FOR MICROELECTROMECHANICAL SYSTEMS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
13901590
|
Filing Dt:
|
05/24/2013
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
Title:
|
METHOD AND APPARATUS FOR SELF-TEST OF SUCCESSIVE APPROXIMATION REGISTER (SAR) A/D CONVERTER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13902872
|
Filing Dt:
|
05/27/2013
|
Publication #:
|
|
Pub Dt:
|
11/27/2014
| | | | |
Title:
|
INTEGRATED CIRCUIT WAKE-UP CONTROL SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
13902873
|
Filing Dt:
|
05/27/2013
|
Title:
|
SYSTEM AND METHOD FOR DETERMINING POWER LEAKAGE OF ELECTRONIC CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13902974
|
Filing Dt:
|
05/27/2013
|
Title:
|
DATA RETENTION FLIP-FLOP
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13905150
|
Filing Dt:
|
05/30/2013
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
SYSTEM FOR PREVENTING TAMPERING WITH INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13905275
|
Filing Dt:
|
05/30/2013
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
I/O CELL ESD SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13906113
|
Filing Dt:
|
05/30/2013
|
Title:
|
SELF ADJUSTING REFERENCE FOR INPUT BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
13907068
|
Filing Dt:
|
05/31/2013
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
OSCILLATOR WITH STARTUP CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
13907484
|
Filing Dt:
|
05/31/2013
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
MULTIPLE DATA RATE MEMORY WITH READ TIMING INFORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13907491
|
Filing Dt:
|
05/31/2013
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
LOGIC TRANSISTOR AND NON-VOLATILE MEMORY CELL INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2015
|
Application #:
|
13910092
|
Filing Dt:
|
06/04/2013
|
Publication #:
|
|
Pub Dt:
|
12/04/2014
| | | | |
Title:
|
METHOD FOR LOW POWER BOOT FOR MICROCONTROLLER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13912170
|
Filing Dt:
|
06/06/2013
|
Title:
|
CLOCK MULTIPLEXER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
13913993
|
Filing Dt:
|
06/10/2013
|
Publication #:
|
|
Pub Dt:
|
12/11/2014
| | | | |
Title:
|
OPTICAL WAFER AND DIE PROBE TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13914021
|
Filing Dt:
|
06/10/2013
|
Publication #:
|
|
Pub Dt:
|
12/11/2014
| | | | |
Title:
|
DIE STACK WITH OPTICAL TSVS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13914049
|
Filing Dt:
|
06/10/2013
|
Publication #:
|
|
Pub Dt:
|
12/11/2014
| | | | |
Title:
|
COMMUNICATION SYSTEM DIE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2016
|
Application #:
|
13914089
|
Filing Dt:
|
06/10/2013
|
Publication #:
|
|
Pub Dt:
|
12/11/2014
| | | | |
Title:
|
INTEGRATION OF A MEMS BEAM WITH OPTICAL WAVEGUIDE AND DEFLECTION IN TWO DIMENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2016
|
Application #:
|
13914123
|
Filing Dt:
|
06/10/2013
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
METHOD AND APPARATUS FOR BEAM CONTROL WITH OPTICAL MEMS BEAM WAVEGUIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
13916146
|
Filing Dt:
|
06/12/2013
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
SYSTEM AND METHOD FOR DEMODULATING AN INCOMING SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13921897
|
Filing Dt:
|
06/19/2013
|
Title:
|
SCALED SIGMA SAMPLING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13925807
|
Filing Dt:
|
06/24/2013
|
Title:
|
SYSTEM AND METHOD FOR LOW-LATENCY ADDRESSING IN FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
13928666
|
Filing Dt:
|
06/27/2013
|
Publication #:
|
|
Pub Dt:
|
01/01/2015
| | | | |
Title:
|
NON-VOLATILE MEMORY (NVM) AND HIGH VOLTAGE TRANSISTOR INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2016
|
Application #:
|
13928671
|
Filing Dt:
|
06/27/2013
|
Publication #:
|
|
Pub Dt:
|
01/01/2015
| | | | |
Title:
|
SYSTEM WITH FEATURE OF SAVING DYNAMIC POWER OF FLIP-FLOP BANKS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13929114
|
Filing Dt:
|
06/27/2013
|
Title:
|
MULTI-LAYER PROCESS-INDUCED DAMAGE TRACKING AND REMEDIATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2016
|
Application #:
|
13930236
|
Filing Dt:
|
06/28/2013
|
Publication #:
|
|
Pub Dt:
|
01/01/2015
| | | | |
Title:
|
DIE-TO-DIE INDUCTIVE COMMUNICATION DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13930657
|
Filing Dt:
|
06/28/2013
|
Publication #:
|
|
Pub Dt:
|
01/01/2015
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS FOR MONITORING FORWARD AND REVERSE BACK BIASING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
13931945
|
Filing Dt:
|
06/30/2013
|
Publication #:
|
|
Pub Dt:
|
01/01/2015
| | | | |
Title:
|
METHOD FOR DETECTING BANK COLLISION AT A MEMORY AND DEVICE THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13935015
|
Filing Dt:
|
07/03/2013
|
Publication #:
|
|
Pub Dt:
|
01/08/2015
| | | | |
Title:
|
USING AN INTEGRATED CIRCUIT DIE CONFIGURATION FOR PACKAGE HEIGHT REDUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
13935552
|
Filing Dt:
|
07/04/2013
|
Publication #:
|
|
Pub Dt:
|
01/08/2015
| | | | |
Title:
|
DIGITAL SELF-GATED BINARY COUNTER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2016
|
Application #:
|
13940644
|
Filing Dt:
|
07/12/2013
|
Publication #:
|
|
Pub Dt:
|
01/15/2015
| | | | |
Title:
|
SYSTEMS AND METHODS FOR REDUCING POWER CONSUMPTION IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
13942814
|
Filing Dt:
|
07/16/2013
|
Publication #:
|
|
Pub Dt:
|
01/22/2015
| | | | |
Title:
|
ADAPTIVE ERASE RECOVERY FOR NON-VOLATILE MEMORY (NVM) SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13944445
|
Filing Dt:
|
07/17/2013
|
Publication #:
|
|
Pub Dt:
|
01/22/2015
| | | | |
Title:
|
WIRE BONDING CAPILLARY WITH WORKING TIP PROTRUSION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13945937
|
Filing Dt:
|
07/19/2013
|
Title:
|
MODULAR GRAY CODE COUNTER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
13953478
|
Filing Dt:
|
07/29/2013
|
Publication #:
|
|
Pub Dt:
|
01/29/2015
| | | | |
Title:
|
METHOD AND SYSTEM FOR FACILITATING VIEWING OF INFORMATION IN A MACHINE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13954205
|
Filing Dt:
|
07/30/2013
|
Publication #:
|
|
Pub Dt:
|
02/05/2015
| | | | |
Title:
|
SPLIT GATE NON-VOLATILE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
13955102
|
Filing Dt:
|
07/31/2013
|
Publication #:
|
|
Pub Dt:
|
02/05/2015
| | | | |
Title:
|
DATA PROCESSOR DEVICE HAVING A DEBUG CONTROL MODULE WHICH SELECTIVELY MODIFIES TRACE MESSAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2016
|
Application #:
|
13955106
|
Filing Dt:
|
07/31/2013
|
Publication #:
|
|
Pub Dt:
|
02/05/2015
| | | | |
Title:
|
SYSTEMS AND METHODS FOR LOCKING BRANCH TARGET BUFFER ENTRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13955665
|
Filing Dt:
|
07/31/2013
|
Title:
|
NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-FIRST METHODOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2016
|
Application #:
|
13956118
|
Filing Dt:
|
07/31/2013
|
Publication #:
|
|
Pub Dt:
|
02/05/2015
| | | | |
Title:
|
DATA PROCESSING SYSTEM WITH PROTOCOL DETERMINATION CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13957075
|
Filing Dt:
|
08/01/2013
|
Publication #:
|
|
Pub Dt:
|
02/05/2015
| | | | |
Title:
|
COUPLER WITH DISTRIBUTED FEEDING AND COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13957449
|
Filing Dt:
|
08/02/2013
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
Title:
|
ELECTRONIC DEVICE FOR DETECTING ERRONOUS KEY SELECTION ENTRY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
13958600
|
Filing Dt:
|
08/04/2013
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
Title:
|
SELF-ADAPTING VOLTAGE AMPLIFIER AND BATTERY CHARGER DETECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13959745
|
Filing Dt:
|
08/06/2013
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
MASTER-SLAVE FLIP-FLOP WITH LOW POWER CONSUMPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13961574
|
Filing Dt:
|
08/07/2013
|
Publication #:
|
|
Pub Dt:
|
12/05/2013
| | | | |
Title:
|
SPLIT GATE MEMORY DEVICE WITH GAP SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13962338
|
Filing Dt:
|
08/08/2013
|
Publication #:
|
|
Pub Dt:
|
02/12/2015
| | | | |
Title:
|
NONVOLATILE MEMORY BITCELL WITH INLAID HIGH K METAL SELECT GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13964110
|
Filing Dt:
|
08/12/2013
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
Title:
|
ELECTRONIC DEVICE WITH POWER MODE CONTROL BUFFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13964119
|
Filing Dt:
|
08/12/2013
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
BASK DEMODULATOR AND METHOD FOR DEMODULATING BASK MODULATED SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13965201
|
Filing Dt:
|
08/13/2013
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
METHOD FOR VERIFYING DIGITAL TO ANALOG CONVERTER DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13965202
|
Filing Dt:
|
08/13/2013
|
Publication #:
|
|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
STATE RETENTION POWER GATED CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
13965731
|
Filing Dt:
|
08/13/2013
|
Publication #:
|
|
Pub Dt:
|
02/19/2015
| | | | |
Title:
|
Extended Protection For Embedded Erase Of Non-Volatile Memory Cells
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
13967337
|
Filing Dt:
|
08/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13969180
|
Filing Dt:
|
08/16/2013
|
Title:
|
NON-VOLATILE MEMORY (NVM) CELL, HIGH VOLTAGE TRANSISTOR, AND HIGH-K AND METAL GATE TRANSISTOR INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2016
|
Application #:
|
13970796
|
Filing Dt:
|
08/20/2013
|
Publication #:
|
|
Pub Dt:
|
02/26/2015
| | | | |
Title:
|
SPLIT-GATE NON-VOLATILE MEMORY CELLS HAVING GAP PROTECTION ZONES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13971007
|
Filing Dt:
|
08/20/2013
|
Title:
|
REDUNDANT SIGNED DIGIT (RSD) ANALOG TO DIGITAL CONVERTER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13971987
|
Filing Dt:
|
08/21/2013
|
Publication #:
|
|
Pub Dt:
|
02/26/2015
| | | | |
Title:
|
INTEGRATED SPLIT GATE NON-VOLATILE MEMORY CELL AND LOGIC STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13972284
|
Filing Dt:
|
08/21/2013
|
Publication #:
|
|
Pub Dt:
|
02/26/2015
| | | | |
Title:
|
LEVEL SHIFTER WITH STATIC PRECHARGE CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
13972372
|
Filing Dt:
|
08/21/2013
|
Publication #:
|
|
Pub Dt:
|
02/26/2015
| | | | |
Title:
|
INTEGRATED SPLIT GATE NON-VOLATILE MEMORY CELL AND LOGIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13972933
|
Filing Dt:
|
08/22/2013
|
Publication #:
|
|
Pub Dt:
|
02/26/2015
| | | | |
Title:
|
DECRYPTION KEY MANAGEMENT SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
13973433
|
Filing Dt:
|
08/22/2013
|
Publication #:
|
|
Pub Dt:
|
02/26/2015
| | | | |
Title:
|
METHOD TO FORM A POLYSILICON NANOCRYSTAL THIN FILM STORAGE BITCELL WITHIN A HIGH K METAL GATE PLATFORM TECHNOLOGY USING A GATE LAST PROCESS TO FORM TRANSISTOR GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13973549
|
Filing Dt:
|
08/22/2013
|
Title:
|
SPLIT-GATE NON-VOLATILE MEMORY (NVM) CELL AND DEVICE STRUCTURE INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13973697
|
Filing Dt:
|
08/22/2013
|
Publication #:
|
|
Pub Dt:
|
02/26/2015
| | | | |
Title:
|
POWER SWITCH WITH CURRENT LIMITATION AND ZERO DIRECT CURRENT (DC) POWER CONSUMPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2015
|
Application #:
|
13988366
|
Filing Dt:
|
05/20/2013
|
Publication #:
|
|
Pub Dt:
|
09/19/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM AND METHOD FOR PREFETCHING LINES OF DATA THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2016
|
Application #:
|
13988425
|
Filing Dt:
|
05/20/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
METHOD FOR ENABLING CALIBRATION DURING START-UP OF A MICRO CONTROLLER UNIT AND INTEGRATED CIRCUIT THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2016
|
Application #:
|
13988821
|
Filing Dt:
|
05/22/2013
|
Publication #:
|
|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
ERROR CORRECTING DEVICE, METHOD FOR MONITORING AN ERROR CORRECTING DEVICE AND DATA PROCESSING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2015
|
Application #:
|
14011160
|
Filing Dt:
|
08/27/2013
|
Publication #:
|
|
Pub Dt:
|
03/05/2015
| | | | |
Title:
|
METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
14013792
|
Filing Dt:
|
08/29/2013
|
Publication #:
|
|
Pub Dt:
|
03/05/2015
| | | | |
Title:
|
ELECTRO-MECHANICAL OSCILLATOR AND COMMON-MODE DETECTION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
14015006
|
Filing Dt:
|
08/30/2013
|
Publication #:
|
|
Pub Dt:
|
03/05/2015
| | | | |
Title:
|
Split Gate Nanocrystal Memory Integration
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2015
|
Application #:
|
14015519
|
Filing Dt:
|
08/30/2013
|
Publication #:
|
|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
CLOCK GLITCH DETECTION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
14016080
|
Filing Dt:
|
08/31/2013
|
Publication #:
|
|
Pub Dt:
|
03/05/2015
| | | | |
Title:
|
METHOD AND CIRCUIT FOR CONTROLLING TURNOFF OF A SEMICONDUCTOR SWITCHING ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2015
|
Application #:
|
14016125
|
Filing Dt:
|
09/01/2013
|
Publication #:
|
|
Pub Dt:
|
03/05/2015
| | | | |
Title:
|
SINGLE PORT MEMORY THAT EMULATES DUAL PORT MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
14017867
|
Filing Dt:
|
09/04/2013
|
Publication #:
|
|
Pub Dt:
|
03/05/2015
| | | | |
Title:
|
EDGE COUPLING OF SEMICONDUCTOR DIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
14021485
|
Filing Dt:
|
09/09/2013
|
Publication #:
|
|
Pub Dt:
|
03/12/2015
| | | | |
Title:
|
Method of Forming Different Voltage Devices with High-K Metal Gate
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
14022646
|
Filing Dt:
|
09/10/2013
|
Publication #:
|
|
Pub Dt:
|
03/12/2015
| | | | |
Title:
|
Methods For Forming Contact Landing Regions In Split-Gate Non-Volatile Memory (NVM) Cell Arrays
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
14022872
|
Filing Dt:
|
09/10/2013
|
Title:
|
MASTER-SLAVE FLIP-FLOP WITH REDUCED SETUP TIME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2015
|
Application #:
|
14023440
|
Filing Dt:
|
09/10/2013
|
Publication #:
|
|
Pub Dt:
|
03/12/2015
| | | | |
Title:
|
NON-VOLATILE MEMORY (NVM) CELL AND HIGH-K AND METAL GATE TRANSISTOR INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
14033622
|
Filing Dt:
|
09/23/2013
|
Publication #:
|
|
Pub Dt:
|
03/26/2015
| | | | |
Title:
|
NON-VOLATILE MEMORY (NVM) WITH DYNAMICALLY ADJUSTED REFERENCE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2016
|
Application #:
|
14034213
|
Filing Dt:
|
09/23/2013
|
Publication #:
|
|
Pub Dt:
|
03/26/2015
| | | | |
Title:
|
STACKED PROTECTION DEVICES AND RELATED FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
14035704
|
Filing Dt:
|
09/24/2013
|
Publication #:
|
|
Pub Dt:
|
03/26/2015
| | | | |
Title:
|
TEMPERATURE DEPENDENT BIASING FOR LEAKAGE POWER REDUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2016
|
Application #:
|
14039562
|
Filing Dt:
|
09/27/2013
|
Publication #:
|
|
Pub Dt:
|
04/02/2015
| | | | |
Title:
|
SYSTEM AND METHOD FOR ENABLING MAXIMUM PERFORMANCE OPERATION WITHIN AN EXTENDED AMBIENT TEMPERATURE RANGE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2015
|
Application #:
|
14041591
|
Filing Dt:
|
09/30/2013
|
Publication #:
|
|
Pub Dt:
|
04/02/2015
| | | | |
Title:
|
NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-LAST METHODOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2015
|
Application #:
|
14041647
|
Filing Dt:
|
09/30/2013
|
Publication #:
|
|
Pub Dt:
|
04/02/2015
| | | | |
Title:
|
NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-FIRST METHODOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
14041662
|
Filing Dt:
|
09/30/2013
|
Title:
|
NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-LAST METHODOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
14041697
|
Filing Dt:
|
09/30/2013
|
Publication #:
|
|
Pub Dt:
|
01/30/2014
| | | | |
Title:
|
DYNAMIC PROGRAMMING FOR FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/2015
|
Application #:
|
14041910
|
Filing Dt:
|
09/30/2013
|
Publication #:
|
|
Pub Dt:
|
04/02/2015
| | | | |
Title:
|
DATA PROCESSING SYSTEM WITH CACHE LINEFILL BUFFER AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
14048362
|
Filing Dt:
|
10/08/2013
|
Publication #:
|
|
Pub Dt:
|
02/06/2014
| | | | |
Title:
|
NON-VOLATILE MEMORY (NVM) WITH IMMINENT ERROR PREDICTION
|
|