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ADAPTER FOR MOUNTING A FACEPLATE OF A FIRST STYLE TO AN ELECTRICAL OUTLET CAVITY OF A SECOND STYLE
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Patent #:
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Issue Dt:
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01/29/2013
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Application #:
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12518905
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Filing Dt:
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06/12/2009
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Publication #:
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Pub Dt:
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02/11/2010
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Title:
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ADAPTIVE ANTENNA SYSTEM FOR DIVERSITY AND INTERFERENCE AVOIDANCE IN A MULTI-STATION NETWORK
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Patent #:
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Issue Dt:
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01/01/2013
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Application #:
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12518961
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Filing Dt:
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06/12/2009
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Publication #:
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Pub Dt:
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01/21/2010
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Title:
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DISTRIBUTED NETWORK MANAGEMENT HIERARCHY IN A MULTI-STATION COMMUNICATION NETWORK
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Patent #:
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Issue Dt:
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03/13/2012
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Application #:
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12533732
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Filing Dt:
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07/31/2009
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Publication #:
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Pub Dt:
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04/15/2010
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Title:
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BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM
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Patent #:
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Issue Dt:
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03/15/2011
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Application #:
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12542296
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Filing Dt:
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08/17/2009
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Publication #:
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Pub Dt:
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12/10/2009
| | | | |
Title:
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DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS
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Patent #:
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Issue Dt:
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05/10/2011
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Application #:
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12542352
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Filing Dt:
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08/17/2009
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Publication #:
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Pub Dt:
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03/11/2010
| | | | |
Title:
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LOW LEAKAGE AND DATA RETENTION CIRCUITRY
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Patent #:
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Issue Dt:
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11/29/2011
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Application #:
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12543839
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Filing Dt:
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08/19/2009
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Publication #:
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Pub Dt:
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02/11/2010
| | | | |
Title:
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DOUBLE DATA RATE OUTPUT LATCH FOR STATIC RAM DEVICE HAS EDGE-TRIGGERED FLIP-FLOP TO OUTPUT DDR SIGNAL TO SYNCHRONIZE WITH A SECOND CLOCK SIGNAL
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Patent #:
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Issue Dt:
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02/05/2013
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Application #:
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12547955
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Filing Dt:
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08/26/2009
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Publication #:
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Pub Dt:
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12/24/2009
| | | | |
Title:
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DELAY LOCKED LOOP IMPLEMENTATION IN A SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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07/17/2012
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Application #:
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12552040
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Filing Dt:
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09/01/2009
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Publication #:
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Pub Dt:
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12/24/2009
| | | | |
Title:
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POWER UP CIRCUIT WITH LOW POWER SLEEP MODE OPERATION
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Patent #:
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Issue Dt:
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02/15/2011
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Application #:
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12553691
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Filing Dt:
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09/03/2009
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Publication #:
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Pub Dt:
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08/05/2010
| | | | |
Title:
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BARRIER-METAL-FREE COPPER DAMASCENE TECHNOLOGY USING ATOMIC HYDROGEN ENHANCED REFLOW
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Patent #:
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Issue Dt:
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11/29/2011
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Application #:
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12564492
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Filing Dt:
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09/22/2009
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Publication #:
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Pub Dt:
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02/10/2011
| | | | |
Title:
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SEMICONDUCTOR MEMORY WITH MULTIPLE WORDLINE SELECTION
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Patent #:
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Issue Dt:
|
12/13/2011
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Application #:
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12566533
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Filing Dt:
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09/24/2009
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Title:
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MIXED COMPOSITION INTERFACE LAYER AND METHOD OF FORMING
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Patent #:
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NONE
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Application #:
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12578115
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Filing Dt:
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10/13/2009
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Publication #:
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Pub Dt:
|
02/04/2010
| | | | |
Title:
|
NONVOLATILE MEMORY SYSTEM
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12607680
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Filing Dt:
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10/28/2009
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Publication #:
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Pub Dt:
|
05/06/2010
| | | | |
Title:
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BRIDGE DEVICE HAVING A VIRTUAL PAGE BUFFER
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Patent #:
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Issue Dt:
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06/05/2012
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Application #:
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12617459
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Filing Dt:
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11/12/2009
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Publication #:
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Pub Dt:
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05/06/2010
| | | | |
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12619157
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Filing Dt:
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11/16/2009
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Publication #:
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Pub Dt:
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03/11/2010
| | | | |
Title:
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TEMPERATURE DETECTOR IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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12/27/2011
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Application #:
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12619238
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Filing Dt:
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11/16/2009
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Publication #:
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Pub Dt:
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01/20/2011
| | | | |
Title:
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SYNCHRONOUS MEMORY READ DATA CAPTURE
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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12619355
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Filing Dt:
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11/16/2009
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Publication #:
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Pub Dt:
|
03/11/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR PACKET PROCESSING
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Patent #:
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Issue Dt:
|
07/19/2011
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Application #:
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12620749
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Filing Dt:
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11/18/2009
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Publication #:
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|
Pub Dt:
|
03/18/2010
| | | | |
Title:
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SYSTEMS AND METHODS FOR MINIMIZING STATIC LEAKAGE OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/12/2011
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Application #:
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12621983
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Filing Dt:
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11/19/2009
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Publication #:
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|
Pub Dt:
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03/11/2010
| | | | |
Title:
|
BIAS GENERATOR PROVIDING FOR LOW POWER, SELF-BIASED DELAY ELEMENT AND DELAY LINE
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Patent #:
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Issue Dt:
|
10/19/2010
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Application #:
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12623899
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Filing Dt:
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11/23/2009
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Publication #:
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Pub Dt:
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06/03/2010
| | | | |
Title:
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METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS
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Patent #:
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Issue Dt:
|
10/28/2014
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Application #:
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12627574
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Filing Dt:
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11/30/2009
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Publication #:
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Pub Dt:
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06/03/2010
| | | | |
Title:
|
NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
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Patent #:
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Issue Dt:
|
03/17/2015
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Application #:
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12627702
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Filing Dt:
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11/30/2009
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Publication #:
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Pub Dt:
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06/03/2010
| | | | |
Title:
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NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
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Patent #:
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Issue Dt:
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10/16/2012
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Application #:
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12627804
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Filing Dt:
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11/30/2009
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Publication #:
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Pub Dt:
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06/03/2010
| | | | |
Title:
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NETWORK COMBINING WIRED AND NON-WIRED SEGMENTS
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Patent #:
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Issue Dt:
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06/28/2011
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Application #:
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12633071
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Filing Dt:
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12/08/2009
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Publication #:
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Pub Dt:
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06/17/2010
| | | | |
Title:
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LOCAL AREA NETWORK OF SERIAL INTELLIGENT CELLS
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Patent #:
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Issue Dt:
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10/25/2011
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Application #:
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12635280
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Filing Dt:
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12/10/2009
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Publication #:
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Pub Dt:
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07/08/2010
| | | | |
Title:
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NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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12638309
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Filing Dt:
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12/15/2009
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Publication #:
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Pub Dt:
|
06/24/2010
| | | | |
Title:
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DELAY LOCKED LOOP CIRCUIT
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Patent #:
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Issue Dt:
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07/10/2012
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Application #:
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12639531
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Filing Dt:
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12/16/2009
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Publication #:
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Pub Dt:
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05/06/2010
| | | | |
Title:
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INITIALIZATION CIRCUIT FOR DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
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06/05/2012
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Application #:
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12640388
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Filing Dt:
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12/17/2009
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Publication #:
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Pub Dt:
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06/24/2010
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH MAIN MEMORY UNIT AND AUXILIARY MEMORY UNIT REQUIRING PRESET OPERATION
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Patent #:
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Issue Dt:
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02/15/2011
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Application #:
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12651707
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Filing Dt:
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01/04/2010
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Publication #:
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Pub Dt:
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04/22/2010
| | | | |
Title:
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MEMORY SYSTEM HAVING INCORRUPTED STROBE SIGNALS
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Patent #:
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Issue Dt:
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04/02/2013
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Application #:
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12652897
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Filing Dt:
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01/06/2010
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Publication #:
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Pub Dt:
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07/08/2010
| | | | |
Title:
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CIRCUIT, SYSTEM AND METHOD FOR SELECTIVELY TURNING OFF INTERNAL CLOCK DRIVERS
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Patent #:
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Issue Dt:
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06/24/2014
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Application #:
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12683731
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Filing Dt:
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01/07/2010
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Publication #:
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Pub Dt:
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04/29/2010
| | | | |
Title:
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TELEPHONE OUTLET WITH PACKET TELEPHONY ADAPTER, AND A NETWORK USING SAME
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Patent #:
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Issue Dt:
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06/26/2012
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Application #:
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12684026
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Filing Dt:
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01/07/2010
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Publication #:
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Pub Dt:
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05/13/2010
| | | | |
Title:
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A DOUBLE DATA RATE CONVERTER CIRCUIT INCLUDES A DELAY LOCKED LOOP FOR PROVIDING THE PLURALITY OF CLOCK PHASE SIGNALS
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Patent #:
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Issue Dt:
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11/22/2011
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12685365
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01/11/2010
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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TERMINATION CIRCUIT FOR ON-DIE TERMINATION
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Patent #:
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Issue Dt:
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06/25/2013
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Application #:
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12685694
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Filing Dt:
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01/12/2010
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
Title:
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TELEPHONE OUTLET WITH PACKET TELEPHONY ADAPTOR, AND A NETWORK USING SAME
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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12687541
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Filing Dt:
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01/14/2010
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Publication #:
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Pub Dt:
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05/13/2010
| | | | |
Title:
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TIMING VERNIER USING A DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
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12/04/2012
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Application #:
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12691794
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Filing Dt:
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01/22/2010
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Publication #:
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Pub Dt:
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05/13/2010
| | | | |
Title:
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VOLTAGE LEVEL SHIFTER AND BUFFER USING SAME
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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12698585
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Filing Dt:
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02/02/2010
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Publication #:
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Pub Dt:
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06/03/2010
| | | | |
Title:
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CIRCUIT AND METHOD FOR TESTING MULTI-DEVICE SYSTEMS
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Patent #:
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Issue Dt:
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03/27/2012
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Application #:
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12699627
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Filing Dt:
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02/03/2010
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Publication #:
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Pub Dt:
|
08/12/2010
| | | | |
Title:
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MEMORY WITH DATA CONTROL
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Patent #:
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Issue Dt:
|
01/11/2011
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Application #:
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12700370
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Filing Dt:
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02/04/2010
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Publication #:
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Pub Dt:
|
06/10/2010
| | | | |
Title:
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PHASE-LOCKED LOOP CIRCUITRY USING CHARGE PUMPS WITH CURRENT MIRROR CIRCUITRY
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Patent #:
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Issue Dt:
|
03/04/2014
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Application #:
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12701122
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Filing Dt:
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02/05/2010
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Publication #:
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Pub Dt:
|
02/17/2011
| | | | |
Title:
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PACKAGE-LEVEL INTEGRATED CIRCUIT CONNECTION WITHOUT TOP METAL PADS OR BONDING WIRE
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