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Total properties:
17
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Patent #:
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Issue Dt:
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06/07/1988
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Application #:
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06838330
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Filing Dt:
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03/10/1986
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Title:
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GRID-BASED, "CROSS-CHECK" TEST STRUCTURE FOR TESTING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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05/08/1990
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Application #:
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07149555
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Filing Dt:
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01/28/1988
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Title:
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STATIC TIMING ANALYSIS OF SEMICONDUCTOR DIGITAL CIRCUITS
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Patent #:
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Issue Dt:
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11/12/1991
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Application #:
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07218724
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Filing Dt:
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07/13/1988
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Title:
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METHOD FOR TESTING INTEGRATED CIRCUITS HAVING A GRID-BASED, "CROSS-CHECK" TEST STRUCTURE
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Patent #:
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Issue Dt:
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06/26/1990
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Application #:
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07242848
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Filing Dt:
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09/09/1988
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Title:
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METHOD AND APPARATUS FOR SENSING DEFECTS IN INTEGRATED CIRCUIT ELEMENTS
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Patent #:
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Issue Dt:
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06/26/1990
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Application #:
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07292620
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Filing Dt:
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12/29/1988
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Title:
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SIMULATION SYSTEM
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Patent #:
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Issue Dt:
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08/06/1991
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Application #:
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07398794
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Filing Dt:
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08/25/1989
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Title:
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METHOD FOR REDUCING MASKING OF ERRORS WHEN USING A GRID-BASED, "CROSS-CHECK" TEST STRUCTURE
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Patent #:
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Issue Dt:
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08/06/1991
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Application #:
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07442282
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Filing Dt:
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11/28/1989
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Title:
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METHOD FOR IMPLEMENTING GRID-BASED CROSSCHECK TEST STRUCTURES AND THE STRUCTURES RESULTING THEREFROM
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Patent #:
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Issue Dt:
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12/04/1990
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Application #:
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07482458
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Filing Dt:
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02/20/1990
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Title:
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METHOD FOR OPERATING A LINEAR FEEDBACK SHIFT REGISTER AS A SERIAL SHIFT REGISTER WITH A CROSSCHECK GRID STRUCTURE
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Patent #:
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Issue Dt:
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10/20/1992
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Application #:
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07554313
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Filing Dt:
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07/17/1990
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Title:
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METHOD AND APPARATUS FOR SETTING DESIRED SIGNAL LEVEL ON STORAGE ELEMENT
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Patent #:
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Issue Dt:
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01/12/1993
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Application #:
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07601969
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Filing Dt:
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10/23/1990
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Title:
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METHOD AND APPARATUS FOR SETTING DESIRED LOGIC STATE AT INTERNAL POINT OF A SELECT STORAGE ELEMENT
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Patent #:
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Issue Dt:
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07/20/1993
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Application #:
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07666538
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Filing Dt:
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03/08/1991
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Title:
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METHOD FOR TESTING A SEQUENTIAL CIRCUIT BY SPLICING TEST VECTORS INTO SEQUENTIAL TEST PATTERN
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Patent #:
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Issue Dt:
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04/27/1993
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Application #:
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07667611
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Filing Dt:
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03/08/1991
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Title:
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METHOD AND APPARATUS FOR LOCALLY DERIVING TEST SIGNALS FROM PREVIOUS RESPONSE SIGNALS
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Patent #:
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Issue Dt:
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04/13/1993
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Application #:
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07744205
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Filing Dt:
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08/12/1991
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Title:
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INTERFACE BETWEEN IC OPERATIONAL CIRCUITRY FOR COUPLING TEST SIGNAL FROM INTERNAL TEST MATRIX
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Patent #:
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Issue Dt:
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02/27/1996
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Application #:
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07929873
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Filing Dt:
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08/11/1992
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|
Title:
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METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/25/1995
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Application #:
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08120148
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Filing Dt:
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09/09/1993
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Title:
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METHOD AND STRUCTURE FOR ROUTING POWER FOR OPTIMUM CELL UTILIZATION WITH TWO AND THREE LEVEL METAL IN A PARTIALLY PREDESIGNED INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/28/1995
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Application #:
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08133588
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Filing Dt:
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10/08/1993
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Title:
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STORAGE ELEMENT FOR DELAY TESTING
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Patent #:
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Issue Dt:
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08/25/1998
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Application #:
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08822383
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Filing Dt:
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03/20/1997
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Title:
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METHOD FOR DIRECT ACCESS TEST OF EMBEDDED CELLS AND CUSTOMIZATION LOGIC
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